forked from OSchip/llvm-project
949570ce39
The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995 |
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| .. | ||
| AArch64.cpp | ||
| AMDGPU.cpp | ||
| ARM.cpp | ||
| AVR.cpp | ||
| Hexagon.cpp | ||
| MSP430.cpp | ||
| Mips.cpp | ||
| MipsArchTree.cpp | ||
| PPC.cpp | ||
| PPC64.cpp | ||
| RISCV.cpp | ||
| SPARCV9.cpp | ||
| X86.cpp | ||
| X86_64.cpp | ||