forked from OSchip/llvm-project
024e319489
This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729 |
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.. | ||
Disassembler | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
README.txt | ||
XCore.h | ||
XCore.td | ||
XCoreAsmPrinter.cpp | ||
XCoreCallingConv.td | ||
XCoreFrameLowering.cpp | ||
XCoreFrameLowering.h | ||
XCoreFrameToArgsOffsetElim.cpp | ||
XCoreISelDAGToDAG.cpp | ||
XCoreISelLowering.cpp | ||
XCoreISelLowering.h | ||
XCoreInstrFormats.td | ||
XCoreInstrInfo.cpp | ||
XCoreInstrInfo.h | ||
XCoreInstrInfo.td | ||
XCoreLowerThreadLocal.cpp | ||
XCoreMCInstLower.cpp | ||
XCoreMCInstLower.h | ||
XCoreMachineFunctionInfo.cpp | ||
XCoreMachineFunctionInfo.h | ||
XCoreRegisterInfo.cpp | ||
XCoreRegisterInfo.h | ||
XCoreRegisterInfo.td | ||
XCoreSelectionDAGInfo.cpp | ||
XCoreSelectionDAGInfo.h | ||
XCoreSubtarget.cpp | ||
XCoreSubtarget.h | ||
XCoreTargetMachine.cpp | ||
XCoreTargetMachine.h | ||
XCoreTargetObjectFile.cpp | ||
XCoreTargetObjectFile.h | ||
XCoreTargetStreamer.h | ||
XCoreTargetTransformInfo.h |
README.txt
To-do ----- * Instruction encodings * Tailcalls * Investigate loop alignment * Add builtins