forked from OSchip/llvm-project
114 lines
3.7 KiB
ArmAsm
114 lines
3.7 KiB
ArmAsm
// REQUIRES: aarch64
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// RUN: split-file %s %t
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// RUN: llvm-mc -filetype=obj -triple=aarch64 %t/asm -o %t.o
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// RUN: ld.lld --script %t/lds --shared %t.o -o %t.so 2>&1
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// RUN: llvm-objdump -d --no-show-raw-insn --print-imm-hex %t.so | FileCheck %s
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// Check that Position Independent thunks are generated for shared libraries.
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//--- asm
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.section .text_low, "ax", %progbits
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.globl low_target
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.type low_target, %function
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low_target:
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// Need thunk to high_target@plt
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bl high_target
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ret
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// CHECK: <low_target>:
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// CHECK-NEXT: d8: bl 0xec <__AArch64ADRPThunk_high_target>
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// CHECK-NEXT: ret
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.hidden low_target2
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.globl low_target2
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.type low_target2, %function
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low_target2:
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// Need thunk to high_target2
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bl high_target2
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// .text_high+8 = high_target2
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bl .text_high+8
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ret
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// CHECK: <low_target2>:
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// CHECK-NEXT: e0: bl 0xf8 <__AArch64ADRPThunk_high_target2>
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// CHECK-NEXT: e4: bl 0x104 <__AArch64ADRPThunk_>
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// CHECK-NEXT: ret
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// Expect range extension thunks for .text_low
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// adrp calculation is (PC + signed immediate) & (!0xfff)
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// CHECK: <__AArch64ADRPThunk_high_target>:
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// CHECK-NEXT: ec: adrp x16, 0x10000000
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// CHECK-NEXT: add x16, x16, #0x40
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// CHECK-NEXT: br x16
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// CHECK: <__AArch64ADRPThunk_high_target2>:
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// CHECK-NEXT: f8: adrp x16, 0x10000000
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// CHECK-NEXT: add x16, x16, #0x8
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// CHECK-NEXT: br x16
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/// Identical to the previous one, but for the target .text_high+8.
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// CHECK: <__AArch64ADRPThunk_>:
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// CHECK-NEXT: 104: adrp x16, 0x10000000
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// CHECK-NEXT: add x16, x16, #0x8
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// CHECK-NEXT: br x16
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.section .text_high, "ax", %progbits
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.globl high_target
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.type high_target, %function
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high_target:
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// No thunk needed as we can reach low_target@plt
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bl low_target
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ret
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// CHECK: <high_target>:
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// CHECK-NEXT: 10000000: bl 0x10000050 <low_target@plt>
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// CHECK-NEXT: ret
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.hidden high_target2
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.globl high_target2
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.type high_target2, %function
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high_target2:
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// Need thunk to low_target
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bl low_target2
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ret
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// CHECK: <high_target2>:
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// CHECK-NEXT: 10000008: bl 0x10000010 <__AArch64ADRPThunk_low_target2>
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// CHECK-NEXT: ret
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// Expect Thunk for .text.high
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// CHECK: <__AArch64ADRPThunk_low_target2>:
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// CHECK-NEXT: 10000010: adrp x16, 0x0
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// CHECK-NEXT: add x16, x16, #0xe0
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// CHECK-NEXT: br x16
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// CHECK: Disassembly of section .plt:
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// CHECK-EMPTY:
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// CHECK-NEXT: <.plt>:
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// CHECK-NEXT: 10000020: stp x16, x30, [sp, #-0x10]!
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// CHECK-NEXT: adrp x16, 0x10000000
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// CHECK-NEXT: ldr x17, [x16, #0x120]
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// CHECK-NEXT: add x16, x16, #0x120
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// CHECK-NEXT: br x17
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// CHECK-NEXT: nop
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// CHECK-NEXT: nop
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// CHECK-NEXT: nop
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// CHECK-EMPTY:
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// CHECK-NEXT: <high_target@plt>:
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// CHECK-NEXT: 10000040: adrp x16, 0x10000000
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// CHECK-NEXT: ldr x17, [x16, #0x128]
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// CHECK-NEXT: add x16, x16, #0x128
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// CHECK-NEXT: br x17
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// CHECK-EMPTY:
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// CHECK-NEXT: <low_target@plt>:
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// CHECK-NEXT: 10000050: adrp x16, 0x10000000
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// CHECK-NEXT: ldr x17, [x16, #0x130]
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// CHECK-NEXT: add x16, x16, #0x130
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// CHECK-NEXT: br x17
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//--- lds
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PHDRS {
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low PT_LOAD FLAGS(0x1 | 0x4);
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high PT_LOAD FLAGS(0x1 | 0x4);
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}
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SECTIONS {
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.text_low : { *(.text_low) } :low
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.text_high 0x10000000 : { *(.text_high) } :high
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}
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