forked from OSchip/llvm-project
67 lines
2.6 KiB
C++
67 lines
2.6 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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// Register the target.
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RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
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RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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///
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SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM,
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bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
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Subtarget(TT, CPU, FS, is64bit),
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DataLayout(Subtarget.getDataLayout()),
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TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
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FrameLowering(Subtarget) {
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}
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bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createSparcISelDag(*this));
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return false;
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}
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel){
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PM.add(createSparcFPMoverPass(*this));
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PM.add(createSparcDelaySlotFillerPass(*this));
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return true;
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}
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS, Reloc::Model RM,
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CodeModel::Model CM)
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: SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) {
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}
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS, Reloc::Model RM,
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CodeModel::Model CM)
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: SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) {
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}
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