.. |
AsmParser
|
[AMDGPU] Update assembler for HSA Code Object v3
|
2018-06-21 19:38:56 +00:00 |
Disassembler
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
InstPrinter
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
MCTargetDesc
|
[AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC)
|
2018-07-10 20:07:22 +00:00 |
TargetInfo
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
Utils
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPU.h
|
AMDGPU: Add pass to lower kernel arguments to loads
|
2018-06-26 19:10:00 +00:00 |
AMDGPU.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUAliasAnalysis.cpp
|
[AMDGPU] Change constant addr space to 4
|
2018-02-13 18:00:25 +00:00 |
AMDGPUAliasAnalysis.h
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-08 23:53:55 +00:00 |
AMDGPUAlwaysInlinePass.cpp
|
Reapply "AMDGPU: Force inlining if LDS global address is used"
|
2018-07-10 14:03:41 +00:00 |
AMDGPUAnnotateKernelFeatures.cpp
|
[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
|
2017-08-31 21:56:16 +00:00 |
AMDGPUAnnotateUniformValues.cpp
|
…
|
|
AMDGPUArgumentUsageInfo.cpp
|
AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
|
2018-06-21 18:36:04 +00:00 |
AMDGPUArgumentUsageInfo.h
|
AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
|
2018-06-21 18:36:04 +00:00 |
AMDGPUAsmPrinter.cpp
|
[AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC)
|
2018-07-10 17:31:32 +00:00 |
AMDGPUAsmPrinter.h
|
[AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC)
|
2018-07-10 20:07:22 +00:00 |
AMDGPUCallLowering.cpp
|
AMDGPU/GlobalISel: Implement custom kernel arg lowering
|
2018-07-05 17:01:20 +00:00 |
AMDGPUCallLowering.h
|
AMDGPU/GlobalISel: Implement custom kernel arg lowering
|
2018-07-05 17:01:20 +00:00 |
AMDGPUCallingConv.td
|
AMDGPU/GlobalISel: Implement custom kernel arg lowering
|
2018-07-05 17:01:20 +00:00 |
AMDGPUCodeGenPrepare.cpp
|
[AMDGPU] Early expansion of 32 bit udiv/urem
|
2018-06-28 15:59:18 +00:00 |
AMDGPUFeatures.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUFrameLowering.cpp
|
…
|
|
AMDGPUFrameLowering.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
AMDGPUGISel.td
|
AMDGPU/GlobalISel: legalize and select 32-bit G_ASHR
|
2018-06-22 02:54:57 +00:00 |
AMDGPUGenRegisterBankInfo.def
|
AMDGPU/GlobalISel: Use a more correct getValueMapping
|
2018-03-01 21:08:51 +00:00 |
AMDGPUHSAMetadataStreamer.cpp
|
AMDGPU/NFC: Use already available explicit kernarg
|
2018-07-11 17:27:17 +00:00 |
AMDGPUHSAMetadataStreamer.h
|
Fix -Wmismatched-tags warning
|
2018-07-10 22:09:33 +00:00 |
AMDGPUISelDAGToDAG.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUISelLowering.cpp
|
AMDGPU: Fix UBSan error caused by r335942
|
2018-07-06 17:16:17 +00:00 |
AMDGPUISelLowering.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUInline.cpp
|
Rename DEBUG macro to LLVM_DEBUG.
|
2018-05-14 12:53:11 +00:00 |
AMDGPUInstrInfo.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUInstrInfo.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUInstrInfo.td
|
[AMDGPU] Convert rcp to rcp_iflag
|
2018-06-27 15:33:33 +00:00 |
AMDGPUInstructionSelector.cpp
|
AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr
|
2018-06-25 16:17:48 +00:00 |
AMDGPUInstructionSelector.h
|
AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr
|
2018-06-25 16:17:48 +00:00 |
AMDGPUInstructions.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUIntrinsicInfo.cpp
|
[AMDGPU] Update includes for intrinsic changes :(
|
2018-06-23 03:05:39 +00:00 |
AMDGPUIntrinsicInfo.h
|
[AMDGPU] Update includes for intrinsic changes :(
|
2018-06-23 03:05:39 +00:00 |
AMDGPUIntrinsics.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPULegalizerInfo.cpp
|
AMDGPU/GlobalISel: Make IMPLICIT_DEF of all sizes < 512 legal.
|
2018-06-30 04:09:44 +00:00 |
AMDGPULegalizerInfo.h
|
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
|
2018-03-08 16:24:16 +00:00 |
AMDGPULibCalls.cpp
|
Rename DEBUG macro to LLVM_DEBUG.
|
2018-05-14 12:53:11 +00:00 |
AMDGPULibFunc.cpp
|
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
|
2017-11-04 17:37:43 +00:00 |
AMDGPULibFunc.h
|
AMDGPU: Fix missing C++ mode comment
|
2018-06-20 19:45:40 +00:00 |
AMDGPULowerIntrinsics.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPULowerKernelArguments.cpp
|
AMDGPU: Don't use struct type for argument layout
|
2018-06-29 17:31:42 +00:00 |
AMDGPULowerKernelAttributes.cpp
|
AMDGPU: Add pass to optimize reqd_work_group_size
|
2018-05-18 21:35:00 +00:00 |
AMDGPUMCInstLower.cpp
|
AMDGPU: Split R600 MCInst lowering into its own class
|
2018-05-29 17:41:59 +00:00 |
AMDGPUMachineCFGStructurizer.cpp
|
Rename DEBUG macro to LLVM_DEBUG.
|
2018-05-14 12:53:11 +00:00 |
AMDGPUMachineFunction.cpp
|
AMDGPU: Remove MFI::ABIArgOffset
|
2018-06-28 10:18:55 +00:00 |
AMDGPUMachineFunction.h
|
AMDGPU: Remove MFI::ABIArgOffset
|
2018-06-28 10:18:55 +00:00 |
AMDGPUMachineModuleInfo.cpp
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
AMDGPUMachineModuleInfo.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
AMDGPUMacroFusion.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
AMDGPUMacroFusion.h
|
…
|
|
AMDGPUOpenCLEnqueuedBlockLowering.cpp
|
[AMDGPU] Change enqueue kernel handle type
|
2018-06-13 17:31:51 +00:00 |
AMDGPUPTNote.h
|
AMDGPU/NFC: Move AMDGPU specific note types to ELF.h
|
2017-10-12 18:59:54 +00:00 |
AMDGPUPerfHintAnalysis.cpp
|
[AMDGPU] Do not consider indirect acces through phi for wave limiter
|
2018-06-11 16:50:49 +00:00 |
AMDGPUPerfHintAnalysis.h
|
Fix -Winconsistent-missing-overrides in AMDGPU code
|
2018-05-25 17:46:24 +00:00 |
AMDGPUPromoteAlloca.cpp
|
Implement strip.invariant.group
|
2018-07-02 04:49:30 +00:00 |
AMDGPURegAsmNames.inc.cpp
|
…
|
|
AMDGPURegisterBankInfo.cpp
|
AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr
|
2018-06-25 16:17:48 +00:00 |
AMDGPURegisterBankInfo.h
|
AMDGPU/GlobalISel: Define instruction mapping for G_OR
|
2018-03-01 21:25:25 +00:00 |
AMDGPURegisterBanks.td
|
AMDGPU/GlobalISel: Define InstrMappings for G_ICMP
|
2018-03-01 19:27:10 +00:00 |
AMDGPURegisterInfo.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
AMDGPURegisterInfo.h
|
AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo
|
2018-05-03 22:38:06 +00:00 |
AMDGPURegisterInfo.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPURewriteOutArguments.cpp
|
Rename DEBUG macro to LLVM_DEBUG.
|
2018-05-14 12:53:11 +00:00 |
AMDGPUSearchableTables.td
|
AMDGPU: Remove old-style image intrinsics
|
2018-06-21 13:37:45 +00:00 |
AMDGPUSubtarget.cpp
|
AMDGPU: Don't use struct type for argument layout
|
2018-06-29 17:31:42 +00:00 |
AMDGPUSubtarget.h
|
AMDGPU: Fix UBSan error caused by r335942
|
2018-07-06 17:16:17 +00:00 |
AMDGPUTargetMachine.cpp
|
Reapply "AMDGPU: Force inlining if LDS global address is used"
|
2018-07-10 14:03:41 +00:00 |
AMDGPUTargetMachine.h
|
Reapply "AMDGPU: Force inlining if LDS global address is used"
|
2018-07-10 14:03:41 +00:00 |
AMDGPUTargetObjectFile.cpp
|
AMDGPU: Fix set but not used warnings related to AMDGPUAS
|
2017-11-01 19:12:38 +00:00 |
AMDGPUTargetObjectFile.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
AMDGPUTargetTransformInfo.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUTargetTransformInfo.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDGPUUnifyDivergentExitNodes.cpp
|
Move Analysis/Utils/Local.h back to Transforms
|
2018-06-04 21:23:21 +00:00 |
AMDGPUUnifyMetadata.cpp
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
AMDILCFGStructurizer.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
AMDKernelCodeT.h
|
Remove @brief commands from doxygen comments, too.
|
2018-05-01 16:10:38 +00:00 |
BUFInstructions.td
|
AMDGPU: Turn D16 for MIMG instructions into a regular operand
|
2018-06-21 13:36:01 +00:00 |
CMakeLists.txt
|
[AMDGPU] Fix layering issue with AMDGPUHSAMetadataStreamer (NFC)
|
2018-07-10 20:07:22 +00:00 |
CaymanInstructions.td
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
DSInstructions.td
|
AMDGPU: Add patterns for i32/i64 local atomic load/store
|
2018-06-22 08:39:52 +00:00 |
EvergreenInstructions.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
FLATInstructions.td
|
AMDGPU: Make various NamedOperands upper case
|
2018-06-04 14:45:20 +00:00 |
GCNHazardRecognizer.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
GCNHazardRecognizer.h
|
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
|
2017-12-07 20:34:25 +00:00 |
GCNILPSched.cpp
|
Rename DEBUG macro to LLVM_DEBUG.
|
2018-05-14 12:53:11 +00:00 |
GCNIterativeScheduler.cpp
|
[AMDGPU] Track occupancy in MFI
|
2018-05-31 05:36:04 +00:00 |
GCNIterativeScheduler.h
|
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
|
2017-11-20 14:35:53 +00:00 |
GCNMinRegStrategy.cpp
|
Rename DEBUG macro to LLVM_DEBUG.
|
2018-05-14 12:53:11 +00:00 |
GCNProcessors.td
|
AMDGPU: Add Vega12 and Vega20
|
2018-04-30 19:08:16 +00:00 |
GCNRegPressure.cpp
|
[AMDGPU] Factored out common part of GCNRPTracker::reset()
|
2018-06-04 17:21:54 +00:00 |
GCNRegPressure.h
|
[AMDGPU] Factored out common part of GCNRPTracker::reset()
|
2018-06-04 17:21:54 +00:00 |
GCNSchedStrategy.cpp
|
[AMDGPU] Small refactoring in the scheduler
|
2018-06-04 17:57:40 +00:00 |
GCNSchedStrategy.h
|
[AMDGPU] Track occupancy in MFI
|
2018-05-31 05:36:04 +00:00 |
LLVMBuild.txt
|
…
|
|
MIMGInstructions.td
|
AMDGPU: Remove redundant MIMG instruction variants
|
2018-06-21 13:37:55 +00:00 |
R600.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600AsmPrinter.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600AsmPrinter.h
|
AMDGPU: Split R600 AsmPrinter code into its own class
|
2018-05-24 20:02:01 +00:00 |
R600ClauseMergePass.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600ControlFlowFinalizer.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600Defines.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
R600EmitClauseMarkers.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600ExpandSpecialInstrs.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600FrameLowering.cpp
|
…
|
|
R600FrameLowering.h
|
AMDGPU: Initial implementation of calls
|
2017-08-01 19:54:18 +00:00 |
R600ISelLowering.cpp
|
AMDGPU: Fix UBSan error caused by r335942
|
2018-07-06 17:16:17 +00:00 |
R600ISelLowering.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600InstrFormats.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600InstrInfo.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600InstrInfo.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600Instructions.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600MachineFunctionInfo.cpp
|
…
|
|
R600MachineFunctionInfo.h
|
…
|
|
R600MachineScheduler.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600MachineScheduler.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
R600OpenCLImageTypeLoweringPass.cpp
|
AMDGPU: Rename OpenCL lowering pass to be R600 specific.
|
2018-05-13 10:04:48 +00:00 |
R600OptimizeVectorRegisters.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600Packetizer.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600Processors.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600RegisterInfo.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600RegisterInfo.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600RegisterInfo.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
R600Schedule.td
|
…
|
|
R700Instructions.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIAnnotateControlFlow.cpp
|
Move Analysis/Utils/Local.h back to Transforms
|
2018-06-04 21:23:21 +00:00 |
SIDebuggerInsertNops.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIDefines.h
|
AMDGPU: Turn D16 for MIMG instructions into a regular operand
|
2018-06-21 13:36:01 +00:00 |
SIFixSGPRCopies.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIFixVGPRCopies.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIFixWWMLiveness.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIFoldOperands.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIFormMemoryClauses.cpp
|
[AMDGPU] Construct memory clauses before RA
|
2018-05-31 20:13:51 +00:00 |
SIFrameLowering.cpp
|
AMDGPU: Pass function directly instead of MachineFunction
|
2018-05-29 17:42:50 +00:00 |
SIFrameLowering.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
SIISelLowering.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIISelLowering.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIInsertSkips.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIInsertWaitcnts.cpp
|
[AMDGPU][Waitcnt] fix "comparison of integers of different signs" build error
|
2018-07-09 19:28:14 +00:00 |
SIInstrFormats.td
|
[AMDGPU] Add VALU to V_INTERP Instructions
|
2018-07-05 12:02:07 +00:00 |
SIInstrInfo.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIInstrInfo.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIInstrInfo.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIInstructions.td
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIIntrinsics.td
|
…
|
|
SILoadStoreOptimizer.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SILowerControlFlow.cpp
|
[AMDGPU] prevent hitting Assertion `isReg() && "Wrong MachineOperand accessor"'
|
2018-06-12 00:41:26 +00:00 |
SILowerI1Copies.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIMachineFunctionInfo.cpp
|
AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
|
2018-06-21 18:36:04 +00:00 |
SIMachineFunctionInfo.h
|
AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z
|
2018-06-21 18:36:04 +00:00 |
SIMachineScheduler.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIMachineScheduler.h
|
Remove \brief commands from doxygen comments.
|
2018-05-01 15:54:18 +00:00 |
SIMemoryLegalizer.cpp
|
[AMDGPU] Simplify memory legalizer (add missing virtual descructor)
|
2018-06-08 01:00:11 +00:00 |
SIOptimizeExecMasking.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIOptimizeExecMaskingPreRA.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIPeepholeSDWA.cpp
|
AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers
|
2018-05-22 02:03:23 +00:00 |
SIProgramInfo.h
|
[AMDGPU] Refactor HSAMetadataStream::emitKernel (NFC)
|
2018-07-10 17:31:32 +00:00 |
SIRegisterInfo.cpp
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIRegisterInfo.h
|
AMDGPU: Separate R600 and GCN TableGen files
|
2018-06-28 23:47:12 +00:00 |
SIRegisterInfo.td
|
AMDGPU: Make v4i16/v4f16 legal
|
2018-06-15 15:15:46 +00:00 |
SISchedule.td
|
[SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639)
|
2018-04-05 13:11:36 +00:00 |
SIShrinkInstructions.cpp
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AMDGPU: Remove AMDGPUMCInstLower.h
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2018-05-25 04:57:02 +00:00 |
SIWholeQuadMode.cpp
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[AMDGPU] Fixed WWM bug in block otherwise entirely in WQM
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2018-05-27 17:26:11 +00:00 |
SMInstructions.td
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[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
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2018-04-06 15:48:39 +00:00 |
SOPInstructions.td
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[AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32
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2018-04-09 13:10:33 +00:00 |
VIInstrFormats.td
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…
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VIInstructions.td
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…
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VOP1Instructions.td
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[AMDGPU] Convert rcp to rcp_iflag
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2018-06-27 15:33:33 +00:00 |
VOP2Instructions.td
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AMDGPU: Add Vega12 and Vega20
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2018-04-30 19:08:16 +00:00 |
VOP3Instructions.td
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[AMDGPU] DAG combine to produce V_PERM_B32
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2018-06-12 23:50:37 +00:00 |
VOP3PInstructions.td
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AMDGPU: Fix v_dot{4, 8}* instruction encoding
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2018-05-15 19:32:47 +00:00 |
VOPCInstructions.td
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[AMDGPU][MC] Corrected default values for unused SDWA operands
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2018-03-16 15:40:27 +00:00 |
VOPInstructions.td
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AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classes
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2018-03-26 13:56:53 +00:00 |