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llvm-project/llvm/lib/Target/RISCV
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Fraser Cormack c5cac48549 [RISCV] Fix lowering of BUILD_VECTORs as VID sequences 
This patch fixes a bug when lowering BUILD_VECTOR via VID sequences.
After adding support for fractional steps in D106533, elements with zero
steps may be skipped if no step has yet been computed. This allowed
certain sequences to slip through the cracks, being identified as VID
sequences when in fact they are not.

The fix for this is to perform a second loop over the BUILD_VECTOR to
validate the entire sequence once the step has been computed. This isn't
the most efficient, but on balance the code is more readable and
maintainable than doing back-validation during the first loop.

Fixes the tests introduced in D123785.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123786
 		2022-04-19 07:43:38 +01:00
..
AsmParser [RISCV] Add a encodeLMUL function to RISCVVType. NFC 2022-04-12 13:39:47 -07:00
Disassembler [Disassember][NFCI] Use strong type for instruction decoder 2022-03-25 18:53:59 -07:00
MCTargetDesc [RISCV][NFC] Use addExpr() instead of createExpr() 2022-04-14 10:48:25 +08:00
TargetInfo Fix shlib builds for all lib/Target/*/TargetInfo libs 2021-10-08 15:21:13 -07:00
CMakeLists.txt [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file 2022-04-08 11:55:48 +08:00
RISCV.h [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.td [RISCV] Remove ExtZvl enum from RISCVSubtarget. NFC 2022-04-11 10:01:17 -07:00
RISCVAsmPrinter.cpp [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute 2022-03-24 00:48:52 +08:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp [RISCV] Fixing stack offset for RVV object with vararg in stack. 2022-04-08 12:01:16 +08:00
RISCVFrameLowering.h Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp [RISCV] Remove unnecessary cast to i8* when converting gather/scatter to strided load/store. 2022-04-09 20:05:03 -07:00
RISCVISelDAGToDAG.cpp [RISCV] Remove sext_inreg+riscv_grev/riscv_gorc isel patterns 2022-04-14 08:16:32 +00:00
RISCVISelDAGToDAG.h [RISCV] Select unmasked RVV pseudos in a DAG post-process 2022-02-09 07:50:15 +00:00
RISCVISelLowering.cpp [RISCV] Fix lowering of BUILD_VECTORs as VID sequences 2022-04-19 07:43:38 +01:00
RISCVISelLowering.h [RISCV] Add rvv codegen support for vp.fptrunc. 2022-04-19 01:56:18 +00:00
RISCVInsertVSETVLI.cpp [RISCV] Use maskedoff to decide mask policy for masked compare and vmsbf/vmsif/vmsof. 2022-03-29 18:05:33 -07:00
RISCVInstrFormats.td [RISCV] Support mask policy for RVV IR intrinsics. 2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Remove Zvamo Extention 2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
RISCVInstrInfo.h [MachineOutliner] NFC: Hide LRU-related stuff behind helper functions 2022-02-16 11:39:07 -08:00
RISCVInstrInfo.td [RISCV][NFC] Add immediate tests for the icmp instruction 2022-03-30 02:51:26 +00:00
RISCVInstrInfoA.td [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage 2022-02-28 14:02:43 +08:00
RISCVInstrInfoC.td [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets 2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoF.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoM.td [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td [RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions 2022-03-31 01:33:17 -07:00
RISCVInstrInfoVPseudos.td [RISCV] Select unmasked integer setcc insts via ISel post-process 2022-04-07 09:30:19 +01:00
RISCVInstrInfoVSDPatterns.td [RISCV][NFC] Refactor patterns for Multiply Add instructions 2022-04-14 08:00:00 +00:00
RISCVInstrInfoVVLPatterns.td [RISCV] Add rvv codegen support for vp.fptrunc. 2022-04-19 01:56:18 +00:00
RISCVInstrInfoZb.td [RISCV] Remove sext_inreg+riscv_grev/riscv_gorc isel patterns 2022-04-14 08:16:32 +00:00
RISCVInstrInfoZfh.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoZk.td [RISCV] Adjust some comments. 2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp [Target] Remove redundant member initialization (NFC) 2022-01-06 22:01:44 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
RISCVMachineFunctionInfo.cpp [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file 2022-04-08 11:55:48 +08:00
RISCVMachineFunctionInfo.h [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file 2022-04-08 11:55:48 +08:00
RISCVMergeBaseOffset.cpp [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments 2022-03-16 20:25:42 +08:00
RISCVRedundantCopyElimination.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp [Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC) 2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h [nfc][codegen] Move RegisterBank[Info].h under CodeGen 2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp Drop some more global std::maps. NFCI. 2022-03-06 13:28:29 +01:00
RISCVRegisterInfo.h [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td [RISCV] add the MC layer support of Zfinx extension 2022-03-02 14:25:19 +08:00
RISCVSExtWRemoval.cpp [RISCV] Add more sign-extending ops to MIR sext.w pass. 2022-03-18 18:21:17 +08:00
RISCVSchedRocket.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVSchedule.td
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RISCVScheduleB.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
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RISCVSubtarget.cpp [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option. 2022-04-11 10:14:48 -07:00
RISCVSubtarget.h [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option. 2022-04-11 10:14:48 -07:00
RISCVSystemOperands.td [RISCV] Initially support the K-extension instructions on the LLVM MC layer 2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file 2022-04-08 11:55:48 +08:00
RISCVTargetMachine.h [RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file 2022-04-08 11:55:48 +08:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option. 2022-04-11 10:14:48 -07:00
RISCVTargetTransformInfo.h [RISCV] Remove riscv-v-fixed-length-vector-elen-max command line option. 2022-04-11 10:14:48 -07:00