forked from OSchip/llvm-project
140 lines
3.6 KiB
C++
140 lines
3.6 KiB
C++
//===-- SIPostRABundler.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass creates bundles of memory instructions to protect adjacent loads
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/// and stores from beeing rescheduled apart from each other post-RA.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-post-ra-bundler"
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namespace {
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class SIPostRABundler : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIPostRABundler() : MachineFunctionPass(ID) {
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initializeSIPostRABundlerPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "SI post-RA bundler";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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const SIRegisterInfo *TRI;
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SmallSet<Register, 16> Defs;
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bool isDependentLoad(const MachineInstr &MI) const;
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIPostRABundler, DEBUG_TYPE, "SI post-RA bundler", false, false)
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char SIPostRABundler::ID = 0;
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char &llvm::SIPostRABundlerID = SIPostRABundler::ID;
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FunctionPass *llvm::createSIPostRABundlerPass() {
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return new SIPostRABundler();
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}
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bool SIPostRABundler::isDependentLoad(const MachineInstr &MI) const {
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if (!MI.mayLoad())
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return false;
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for (const MachineOperand &Op : MI.explicit_operands()) {
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if (!Op.isReg())
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continue;
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Register Reg = Op.getReg();
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for (Register Def : Defs)
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if (TRI->regsOverlap(Reg, Def))
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return true;
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}
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return false;
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}
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bool SIPostRABundler::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
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bool Changed = false;
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const uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF |
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SIInstrFlags::SMRD | SIInstrFlags::DS |
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SIInstrFlags::FLAT | SIInstrFlags::MIMG;
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::instr_iterator Next;
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MachineBasicBlock::instr_iterator B = MBB.instr_begin();
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MachineBasicBlock::instr_iterator E = MBB.instr_end();
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for (auto I = B; I != E; I = Next) {
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Next = std::next(I);
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const uint64_t IMemFlags = I->getDesc().TSFlags & MemFlags;
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if (IMemFlags == 0 || I->isBundled() || !I->mayLoadOrStore() ||
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B->mayLoad() != I->mayLoad() || B->mayStore() != I->mayStore() ||
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((B->getDesc().TSFlags & MemFlags) != IMemFlags) ||
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isDependentLoad(*I)) {
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if (B != I) {
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if (std::next(B) != I) {
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finalizeBundle(MBB, B, I);
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Changed = true;
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}
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Next = I;
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}
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B = Next;
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Defs.clear();
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continue;
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}
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if (I->getNumExplicitDefs() == 0)
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continue;
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Defs.insert(I->defs().begin()->getReg());
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}
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if (B != E && std::next(B) != E) {
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finalizeBundle(MBB, B, E);
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Changed = true;
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}
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Defs.clear();
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}
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return Changed;
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}
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