forked from OSchip/llvm-project
c7334a146e
elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482 |
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| .. | ||
| ARM | ||
| Alpha | ||
| Blackfin | ||
| CBackend | ||
| CPP | ||
| CellSPU | ||
| Generic | ||
| MBlaze | ||
| MSP430 | ||
| Mips | ||
| PTX | ||
| PowerPC | ||
| SPARC | ||
| SystemZ | ||
| Thumb | ||
| Thumb2 | ||
| X86 | ||
| XCore | ||
| thumb2-mul.ll | ||