..
AArch64
Tighten up DIFile verifier for checksums
2018-01-11 22:03:43 +00:00
AMDGPU
AMDGPU/SI: Add d16 support for buffer intrinsics.
2018-01-12 21:12:19 +00:00
ARM
[ARM] Issue an erorr when non-general-purpose registers are used in address operands
2018-01-05 13:28:10 +00:00
AVR
[AVR] Implement some missing code paths
2017-12-11 11:01:27 +00:00
AsmParser
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
BPF
bpf: print backward branch target properly
2017-11-16 19:15:36 +00:00
COFF
Reland "Emit Function IDs table for Control Flow Guard"
2018-01-09 23:49:30 +00:00
Disassembler
[X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.
2018-01-12 06:21:36 +00:00
ELF
[DWARFv5] MC support for MD5 file checksums
2018-01-09 23:31:48 +00:00
Hexagon
[Hexagon] Add support for Hexagon V65
2017-12-11 18:57:54 +00:00
Lanai
[lanai] Add more tests for assembly of conditional ALU ops
2016-07-11 17:58:16 +00:00
MachO
[X86] Don't use NOPL when the assembler is passed an empty CPU string. Update tests to force a CPU with NOPL
2017-12-18 21:37:27 +00:00
Markup
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Mips
[Mips] Handle one byte unsupported relocations
2018-01-11 10:07:47 +00:00
PowerPC
[PowerPC, AsmParser] Enable the mnemonic spell corrector
2017-12-16 02:42:18 +00:00
RISCV
[RISCV] Pass MCSubtargetInfo to print methods.
2018-01-12 02:27:00 +00:00
Sparc
[Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed
2017-07-25 15:28:28 +00:00
SystemZ
[SystemZ, AsmParser] Enable the mnemonic spell corrector.
2017-07-18 09:17:00 +00:00
WebAssembly
[WebAssemlby] MC: Don't write COMDAT symbols as global imports
2018-01-11 20:35:17 +00:00
X86
[X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 bits isa sets.<NFC>
2018-01-15 09:39:08 +00:00