llvm-project/llvm/test/CodeGen
Chandler Carruth e7e9c04ddf [x86] Teach the instruction lowering to add comments describing constant
pool data being loaded into a vector register.

The comments take the form of:

  # ymm0 = [a,b,c,d,...]
  # xmm1 = <x,y,z...>

The []s are used for generic sequential data and the <>s are used for
specifically ConstantVector loads. Undef elements are printed as the
letter 'u', integers in decimal, and floating point values as floating
point values. Suggestions on improving the formatting or other aspects
of the display are very welcome.

My primary use case for this is to be able to FileCheck test masks
passed to vector shuffle instructions in-register. It isn't fantastic
for that (no decoding special zeroing semantics or other tricks), but it
at least puts the mask onto an instruction line that could reasonably be
checked. I've updated many of the new vector shuffle lowering tests to
leverage this in their test cases so that we're actually checking the
shuffle masks remain as expected.

Before implementing this, I tried a *bunch* of different approaches.
I looked into teaching the MCInstLower code to scan up the basic block
and find a definition of a register used in a shuffle instruction and
then decode that, but this seems incredibly brittle and complex.
I talked to Hal a lot about the "right" way to do this: attach the raw
shuffle mask to the instruction itself in some form of unencoded
operands, and then use that to emit the comments. I still think that's
the optimal solution here, but it proved to be beyond what I'm up for
here. In particular, it seems likely best done by completing the
plumbing of metadata through these layers and attaching the shuffle mask
in metadata which could have fully automatic dropping when encoding an
actual instruction.

llvm-svn: 218377
2014-09-24 09:39:41 +00:00
..
AArch64 [FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1). 2014-09-22 21:08:53 +00:00
ARM Fix swift-atomics testcase 2014-09-23 23:18:01 +00:00
CPP IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Generic Fix crash with an insertvalue that produces an empty object. 2014-09-20 00:10:47 +00:00
Hexagon DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range. 2014-08-06 00:21:25 +00:00
Inputs
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
Mips Add mips32 r1 to the list of supported targets for Mips fast-isel 2014-09-15 20:30:25 +00:00
NVPTX [MachineSink] Use the real post dominator tree 2014-09-01 03:47:25 +00:00
PowerPC [Power] Use AtomicExpandPass for fence insertion, and use lwsync where appropriate 2014-09-23 20:46:49 +00:00
R600 R600/SI: Fix weird CHECK-DAG usage 2014-09-24 02:14:26 +00:00
SPARC Add back tests for empty function in SPARC and PowerPC. 2014-09-15 22:11:07 +00:00
SystemZ IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Thumb Check-label a bit more specific 2014-09-03 13:32:08 +00:00
Thumb2 ARM / x86_64 varargs: Don't save regparms in prologue without va_start 2014-08-22 21:59:26 +00:00
X86 [x86] Teach the instruction lowering to add comments describing constant 2014-09-24 09:39:41 +00:00
XCore llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32. 2014-07-04 11:58:03 +00:00