forked from OSchip/llvm-project
568 lines
20 KiB
TableGen
568 lines
20 KiB
TableGen
//===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the BPF instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "BPFInstrFormats.td"
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// Instruction Operands and Patterns
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// These are target-independent nodes, but have target-specific formats.
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def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
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SDTCisVT<1, iPTR>]>;
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def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
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def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
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SDTCisSameAs<0, 4>,
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SDTCisSameAs<4, 5>]>;
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def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
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SDTCisVT<3, OtherVT>]>;
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def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<0>]>;
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def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
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[SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
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def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
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def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
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def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">;
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def BPFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i64>;
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def u64imm : Operand<i64> {
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let PrintMethod = "printImm64Operand";
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}
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def i64immSExt32 : PatLeaf<(i64 imm),
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[{return isInt<32>(N->getSExtValue()); }]>;
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// Addressing modes.
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def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
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def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
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// Address operands
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def MEMri : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let EncoderMethod = "getMemoryOpValue";
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let DecoderMethod = "decodeMemoryOpValue";
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let MIOperandInfo = (ops GPR, i16imm);
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}
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// Conditional code predicates - used for pattern matching for jump instructions
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def BPF_CC_EQ : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETEQ);}]>;
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def BPF_CC_NE : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETNE);}]>;
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def BPF_CC_GE : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETGE);}]>;
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def BPF_CC_GT : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETGT);}]>;
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def BPF_CC_GTU : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETUGT);}]>;
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def BPF_CC_GEU : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETUGE);}]>;
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def BPF_CC_LE : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETLE);}]>;
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def BPF_CC_LT : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETLT);}]>;
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def BPF_CC_LTU : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETULT);}]>;
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def BPF_CC_LEU : PatLeaf<(i64 imm),
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[{return (N->getZExtValue() == ISD::SETULE);}]>;
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// For arithmetic and jump instructions the 8-bit 'code'
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// field is divided into three parts:
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//
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// +----------------+--------+--------------------+
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// | 4 bits | 1 bit | 3 bits |
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// | operation code | source | instruction class |
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// +----------------+--------+--------------------+
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// (MSB) (LSB)
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class TYPE_ALU_JMP<bits<4> op, bits<1> srctype,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstBPF<outs, ins, asmstr, pattern> {
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let Inst{63-60} = op;
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let Inst{59} = srctype;
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}
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//For load and store instructions the 8-bit 'code' field is divided as:
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//
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// +--------+--------+-------------------+
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// | 3 bits | 2 bits | 3 bits |
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// | mode | size | instruction class |
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// +--------+--------+-------------------+
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// (MSB) (LSB)
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class TYPE_LD_ST<bits<3> mode, bits<2> size,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstBPF<outs, ins, asmstr, pattern> {
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let Inst{63-61} = mode;
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let Inst{60-59} = size;
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}
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// jump instructions
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class JMP_RR<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
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: TYPE_ALU_JMP<Opc.Value, BPF_X.Value,
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(outs),
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(ins GPR:$dst, GPR:$src, brtarget:$BrDst),
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"if $dst "#OpcodeStr#" $src goto $BrDst",
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[(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
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bits<4> dst;
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bits<4> src;
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bits<16> BrDst;
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let Inst{55-52} = src;
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let Inst{51-48} = dst;
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let Inst{47-32} = BrDst;
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let BPFClass = BPF_JMP;
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}
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class JMP_RI<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond>
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: TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
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(outs),
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(ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
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"if $dst "#OpcodeStr#" $imm goto $BrDst",
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[(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
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bits<4> dst;
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bits<16> BrDst;
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bits<32> imm;
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let Inst{51-48} = dst;
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let Inst{47-32} = BrDst;
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let Inst{31-0} = imm;
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let BPFClass = BPF_JMP;
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}
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multiclass J<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> {
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def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
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def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
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}
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let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
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// cmp+goto instructions
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defm JEQ : J<BPF_JEQ, "==", BPF_CC_EQ>;
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defm JUGT : J<BPF_JGT, ">", BPF_CC_GTU>;
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defm JUGE : J<BPF_JGE, ">=", BPF_CC_GEU>;
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defm JNE : J<BPF_JNE, "!=", BPF_CC_NE>;
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defm JSGT : J<BPF_JSGT, "s>", BPF_CC_GT>;
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defm JSGE : J<BPF_JSGE, "s>=", BPF_CC_GE>;
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defm JULT : J<BPF_JLT, "<", BPF_CC_LTU>;
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defm JULE : J<BPF_JLE, "<=", BPF_CC_LEU>;
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defm JSLT : J<BPF_JSLT, "s<", BPF_CC_LT>;
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defm JSLE : J<BPF_JSLE, "s<=", BPF_CC_LE>;
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}
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// ALU instructions
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class ALU_RI<BPFOpClass Class, BPFArithOp Opc,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: TYPE_ALU_JMP<Opc.Value, BPF_K.Value, outs, ins, asmstr, pattern> {
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bits<4> dst;
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bits<32> imm;
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let Inst{51-48} = dst;
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let Inst{31-0} = imm;
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let BPFClass = Class;
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}
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class ALU_RR<BPFOpClass Class, BPFArithOp Opc,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: TYPE_ALU_JMP<Opc.Value, BPF_X.Value, outs, ins, asmstr, pattern> {
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bits<4> dst;
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bits<4> src;
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let Inst{55-52} = src;
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let Inst{51-48} = dst;
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let BPFClass = Class;
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}
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multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
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def _rr : ALU_RR<BPF_ALU64, Opc,
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(outs GPR:$dst),
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(ins GPR:$src2, GPR:$src),
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"$dst "#OpcodeStr#" $src",
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[(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
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def _ri : ALU_RI<BPF_ALU64, Opc,
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(outs GPR:$dst),
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(ins GPR:$src2, i64imm:$imm),
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"$dst "#OpcodeStr#" $imm",
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[(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
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def _rr_32 : ALU_RR<BPF_ALU, Opc,
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(outs GPR32:$dst),
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(ins GPR32:$src2, GPR32:$src),
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"$dst "#OpcodeStr#" $src",
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[(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
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def _ri_32 : ALU_RI<BPF_ALU, Opc,
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(outs GPR32:$dst),
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(ins GPR32:$src2, i32imm:$imm),
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"$dst "#OpcodeStr#" $imm",
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[(set GPR32:$dst, (OpNode GPR32:$src2, i32:$imm))]>;
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}
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let Constraints = "$dst = $src2" in {
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let isAsCheapAsAMove = 1 in {
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defm ADD : ALU<BPF_ADD, "+=", add>;
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defm SUB : ALU<BPF_SUB, "-=", sub>;
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defm OR : ALU<BPF_OR, "|=", or>;
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defm AND : ALU<BPF_AND, "&=", and>;
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defm SLL : ALU<BPF_LSH, "<<=", shl>;
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defm SRL : ALU<BPF_RSH, ">>=", srl>;
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defm XOR : ALU<BPF_XOR, "^=", xor>;
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defm SRA : ALU<BPF_ARSH, "s>>=", sra>;
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}
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defm MUL : ALU<BPF_MUL, "*=", mul>;
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defm DIV : ALU<BPF_DIV, "/=", udiv>;
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}
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class NEG_RR<BPFOpClass Class, BPFArithOp Opc,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: TYPE_ALU_JMP<Opc.Value, 0, outs, ins, asmstr, pattern> {
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bits<4> dst;
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let Inst{51-48} = dst;
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let BPFClass = Class;
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}
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let Constraints = "$dst = $src", isAsCheapAsAMove = 1 in {
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def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src),
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"$dst = -$src",
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[(set GPR:$dst, (ineg i64:$src))]>;
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def NEG_32: NEG_RR<BPF_ALU, BPF_NEG, (outs GPR32:$dst), (ins GPR32:$src),
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"$dst = -$src",
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[(set GPR32:$dst, (ineg i32:$src))]>;
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}
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class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
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: TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
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(outs GPR:$dst),
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(ins u64imm:$imm),
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"$dst "#OpcodeStr#" ${imm} ll",
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[(set GPR:$dst, (i64 imm:$imm))]> {
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bits<4> dst;
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bits<64> imm;
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let Inst{51-48} = dst;
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let Inst{55-52} = Pseudo;
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let Inst{47-32} = 0;
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let Inst{31-0} = imm{31-0};
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let BPFClass = BPF_LD;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def LD_imm64 : LD_IMM64<0, "=">;
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def MOV_rr : ALU_RR<BPF_ALU64, BPF_MOV,
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(outs GPR:$dst),
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(ins GPR:$src),
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"$dst = $src",
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[]>;
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def MOV_ri : ALU_RI<BPF_ALU64, BPF_MOV,
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(outs GPR:$dst),
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(ins i64imm:$imm),
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"$dst = $imm",
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[(set GPR:$dst, (i64 i64immSExt32:$imm))]>;
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def MOV_rr_32 : ALU_RR<BPF_ALU, BPF_MOV,
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(outs GPR32:$dst),
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(ins GPR32:$src),
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"$dst = $src",
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[]>;
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def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV,
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(outs GPR32:$dst),
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(ins i32imm:$imm),
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"$dst = $imm",
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[(set GPR32:$dst, (i32 i32:$imm))]>;
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}
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def FI_ri
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: TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
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(outs GPR:$dst),
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(ins MEMri:$addr),
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"lea\t$dst, $addr",
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[(set i64:$dst, FIri:$addr)]> {
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// This is a tentative instruction, and will be replaced
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// with MOV_rr and ADD_ri in PEI phase
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let Inst{51-48} = 0;
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let Inst{55-52} = 2;
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let Inst{47-32} = 0;
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let Inst{31-0} = 0;
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let BPFClass = BPF_LD;
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}
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def LD_pseudo
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: TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value,
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(outs GPR:$dst),
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(ins i64imm:$pseudo, u64imm:$imm),
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"ld_pseudo\t$dst, $pseudo, $imm",
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[(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
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bits<4> dst;
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bits<64> imm;
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bits<4> pseudo;
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let Inst{51-48} = dst;
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let Inst{55-52} = pseudo;
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let Inst{47-32} = 0;
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let Inst{31-0} = imm{31-0};
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let BPFClass = BPF_LD;
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}
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// STORE instructions
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class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
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: TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
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(outs),
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(ins GPR:$src, MEMri:$addr),
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"*("#OpcodeStr#" *)($addr) = $src",
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Pattern> {
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bits<4> src;
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bits<20> addr;
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let Inst{51-48} = addr{19-16}; // base reg
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let Inst{55-52} = src;
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let Inst{47-32} = addr{15-0}; // offset
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let BPFClass = BPF_STX;
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}
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class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
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: STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
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def STW : STOREi64<BPF_W, "u32", truncstorei32>;
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def STH : STOREi64<BPF_H, "u16", truncstorei16>;
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def STB : STOREi64<BPF_B, "u8", truncstorei8>;
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def STD : STOREi64<BPF_DW, "u64", store>;
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// LOAD instructions
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class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern>
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: TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value,
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(outs GPR:$dst),
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(ins MEMri:$addr),
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"$dst = *("#OpcodeStr#" *)($addr)",
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Pattern> {
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bits<4> dst;
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bits<20> addr;
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let Inst{51-48} = dst;
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let Inst{55-52} = addr{19-16};
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let Inst{47-32} = addr{15-0};
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let BPFClass = BPF_LDX;
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}
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class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
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: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
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def LDW : LOADi64<BPF_W, "u32", zextloadi32>;
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def LDH : LOADi64<BPF_H, "u16", zextloadi16>;
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def LDB : LOADi64<BPF_B, "u8", zextloadi8>;
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def LDD : LOADi64<BPF_DW, "u64", load>;
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class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern>
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: TYPE_ALU_JMP<Opc.Value, BPF_K.Value,
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(outs),
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(ins brtarget:$BrDst),
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!strconcat(OpcodeStr, " $BrDst"),
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Pattern> {
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bits<16> BrDst;
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let Inst{47-32} = BrDst;
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let BPFClass = BPF_JMP;
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}
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class CALL<string OpcodeStr>
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: TYPE_ALU_JMP<BPF_CALL.Value, BPF_K.Value,
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(outs),
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(ins calltarget:$BrDst),
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!strconcat(OpcodeStr, " $BrDst"),
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[]> {
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bits<32> BrDst;
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let Inst{31-0} = BrDst;
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let BPFClass = BPF_JMP;
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}
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// Jump always
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let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
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def JMP : BRANCH<BPF_JA, "goto", [(br bb:$BrDst)]>;
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}
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// Jump and link
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let isCall=1, hasDelaySlot=0, Uses = [R11],
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// Potentially clobbered registers
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Defs = [R0, R1, R2, R3, R4, R5] in {
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def JAL : CALL<"call">;
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}
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class NOP_I<string OpcodeStr>
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: TYPE_ALU_JMP<BPF_MOV.Value, BPF_X.Value,
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(outs),
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(ins i32imm:$imm),
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!strconcat(OpcodeStr, "\t$imm"),
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[]> {
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// mov r0, r0 == nop
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let Inst{55-52} = 0;
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let Inst{51-48} = 0;
|
|
let BPFClass = BPF_ALU64;
|
|
}
|
|
|
|
let hasSideEffects = 0 in
|
|
def NOP : NOP_I<"nop">;
|
|
|
|
class RET<string OpcodeStr>
|
|
: TYPE_ALU_JMP<BPF_EXIT.Value, BPF_K.Value,
|
|
(outs),
|
|
(ins),
|
|
!strconcat(OpcodeStr, ""),
|
|
[(BPFretflag)]> {
|
|
let Inst{31-0} = 0;
|
|
let BPFClass = BPF_JMP;
|
|
}
|
|
|
|
let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
|
|
isNotDuplicable = 1 in {
|
|
def RET : RET<"exit">;
|
|
}
|
|
|
|
// ADJCALLSTACKDOWN/UP pseudo insns
|
|
let Defs = [R11], Uses = [R11] in {
|
|
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
|
|
"#ADJCALLSTACKDOWN $amt1 $amt2",
|
|
[(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
|
|
def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
|
|
"#ADJCALLSTACKUP $amt1 $amt2",
|
|
[(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
|
|
}
|
|
|
|
let usesCustomInserter = 1 in {
|
|
def Select : Pseudo<(outs GPR:$dst),
|
|
(ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
|
|
"# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
|
|
[(set i64:$dst,
|
|
(BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
|
|
def Select_Ri : Pseudo<(outs GPR:$dst),
|
|
(ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
|
|
"# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
|
|
[(set i64:$dst,
|
|
(BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>;
|
|
}
|
|
|
|
// load 64-bit global addr into register
|
|
def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
|
|
|
|
// 0xffffFFFF doesn't fit into simm32, optimize common case
|
|
def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
|
|
(SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
|
|
|
|
// Calls
|
|
def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
|
|
def : Pat<(BPFcall texternalsym:$dst), (JAL texternalsym:$dst)>;
|
|
def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
|
|
|
|
// Loads
|
|
def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>;
|
|
def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
|
|
def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
|
|
|
|
// Atomics
|
|
class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
|
|
: TYPE_LD_ST<BPF_XADD.Value, SizeOp.Value,
|
|
(outs GPR:$dst),
|
|
(ins MEMri:$addr, GPR:$val),
|
|
"lock *("#OpcodeStr#" *)($addr) += $val",
|
|
[(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
|
|
bits<4> dst;
|
|
bits<20> addr;
|
|
|
|
let Inst{51-48} = addr{19-16}; // base reg
|
|
let Inst{55-52} = dst;
|
|
let Inst{47-32} = addr{15-0}; // offset
|
|
let BPFClass = BPF_STX;
|
|
}
|
|
|
|
let Constraints = "$dst = $val" in {
|
|
def XADD32 : XADD<BPF_W, "u32", atomic_load_add_32>;
|
|
def XADD64 : XADD<BPF_DW, "u64", atomic_load_add_64>;
|
|
// undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
|
|
// undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
|
|
}
|
|
|
|
// bswap16, bswap32, bswap64
|
|
class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern>
|
|
: TYPE_ALU_JMP<BPF_END.Value, SrcType.Value,
|
|
(outs GPR:$dst),
|
|
(ins GPR:$src),
|
|
"$dst = "#OpcodeStr#" $src",
|
|
Pattern> {
|
|
bits<4> dst;
|
|
|
|
let Inst{51-48} = dst;
|
|
let Inst{31-0} = SizeOp;
|
|
let BPFClass = BPF_ALU;
|
|
}
|
|
|
|
|
|
let Constraints = "$dst = $src" in {
|
|
let Predicates = [BPFIsLittleEndian] in {
|
|
def BE16 : BSWAP<16, "be16", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
|
|
def BE32 : BSWAP<32, "be32", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
|
|
def BE64 : BSWAP<64, "be64", BPF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>;
|
|
}
|
|
let Predicates = [BPFIsBigEndian] in {
|
|
def LE16 : BSWAP<16, "le16", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
|
|
def LE32 : BSWAP<32, "le32", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
|
|
def LE64 : BSWAP<64, "le64", BPF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>;
|
|
}
|
|
}
|
|
|
|
let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
|
|
hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
|
|
class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
|
|
: TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value,
|
|
(outs),
|
|
(ins GPR:$skb, i64imm:$imm),
|
|
"r0 = *("#OpcodeStr#" *)skb[$imm]",
|
|
[(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
|
|
bits<32> imm;
|
|
|
|
let Inst{31-0} = imm;
|
|
let BPFClass = BPF_LD;
|
|
}
|
|
|
|
class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode>
|
|
: TYPE_LD_ST<BPF_IND.Value, SizeOp.Value,
|
|
(outs),
|
|
(ins GPR:$skb, GPR:$val),
|
|
"r0 = *("#OpcodeStr#" *)skb[$val]",
|
|
[(set R0, (OpNode GPR:$skb, GPR:$val))]> {
|
|
bits<4> val;
|
|
|
|
let Inst{55-52} = val;
|
|
let BPFClass = BPF_LD;
|
|
}
|
|
}
|
|
|
|
def LD_ABS_B : LOAD_ABS<BPF_B, "u8", int_bpf_load_byte>;
|
|
def LD_ABS_H : LOAD_ABS<BPF_H, "u16", int_bpf_load_half>;
|
|
def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>;
|
|
|
|
def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>;
|
|
def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>;
|
|
def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>;
|