forked from OSchip/llvm-project
285 lines
9.7 KiB
C++
285 lines
9.7 KiB
C++
//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Hexagon specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMCTargetDesc.h"
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#include "Hexagon.h"
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#include "HexagonMCAsmInfo.h"
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#include "HexagonMCELFStreamer.h"
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#include "MCTargetDesc/HexagonInstPrinter.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "HexagonGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "HexagonGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "HexagonGenRegisterInfo.inc"
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cl::opt<bool> llvm::HexagonDisableCompound
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("mno-compound",
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cl::desc("Disable looking for compound instructions for Hexagon"));
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cl::opt<bool> llvm::HexagonDisableDuplex
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("mno-pairing",
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cl::desc("Disable looking for duplex instructions for Hexagon"));
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static cl::opt<bool> HexagonV4ArchVariant("mv4", cl::Hidden, cl::init(false),
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cl::desc("Build for Hexagon V4"));
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static cl::opt<bool> HexagonV5ArchVariant("mv5", cl::Hidden, cl::init(false),
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cl::desc("Build for Hexagon V5"));
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static cl::opt<bool> HexagonV55ArchVariant("mv55", cl::Hidden, cl::init(false),
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cl::desc("Build for Hexagon V55"));
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static cl::opt<bool> HexagonV60ArchVariant("mv60", cl::Hidden, cl::init(false),
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cl::desc("Build for Hexagon V60"));
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static StringRef DefaultArch = "hexagonv60";
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static StringRef HexagonGetArchVariant() {
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if (HexagonV4ArchVariant)
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return "hexagonv4";
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if (HexagonV5ArchVariant)
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return "hexagonv5";
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if (HexagonV55ArchVariant)
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return "hexagonv55";
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if (HexagonV60ArchVariant)
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return "hexagonv60";
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return "";
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}
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StringRef HEXAGON_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) {
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StringRef ArchV = HexagonGetArchVariant();
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if (!ArchV.empty() && !CPU.empty()) {
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if (ArchV != CPU)
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report_fatal_error("conflicting architectures specified.");
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return CPU;
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}
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if (ArchV.empty()) {
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if (CPU.empty())
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CPU = DefaultArch;
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return CPU;
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}
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return ArchV;
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}
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MCInstrInfo *llvm::createHexagonMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitHexagonMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitHexagonMCRegisterInfo(X, Hexagon::R31);
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return X;
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}
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static MCSubtargetInfo *
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createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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CPU = HEXAGON_MC::selectHexagonCPU(TT, CPU);
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return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
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}
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namespace {
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class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
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public:
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HexagonTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &, bool,
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MCInstPrinter &)
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: HexagonTargetStreamer(S) {}
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void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
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const MCInst &Inst, const MCSubtargetInfo &STI) override {
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assert(HexagonMCInstrInfo::isBundle(Inst));
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assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
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std::string Buffer;
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{
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raw_string_ostream TempStream(Buffer);
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InstPrinter.printInst(&Inst, TempStream, "", STI);
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}
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StringRef Contents(Buffer);
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auto PacketBundle = Contents.rsplit('\n');
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auto HeadTail = PacketBundle.first.split('\n');
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StringRef Separator = "\n";
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StringRef Indent = "\t\t";
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OS << "\t{\n";
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while (!HeadTail.first.empty()) {
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StringRef InstTxt;
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auto Duplex = HeadTail.first.split('\v');
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if (!Duplex.second.empty()) {
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OS << Indent << Duplex.first << Separator;
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InstTxt = Duplex.second;
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} else if (!HeadTail.first.trim().startswith("immext")) {
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InstTxt = Duplex.first;
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}
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if (!InstTxt.empty())
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OS << Indent << InstTxt << Separator;
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HeadTail = HeadTail.second.split('\n');
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}
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OS << "\t}" << PacketBundle.second;
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}
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};
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}
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namespace {
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class HexagonTargetELFStreamer : public HexagonTargetStreamer {
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public:
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MCELFStreamer &getStreamer() {
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return static_cast<MCELFStreamer &>(Streamer);
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}
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HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
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: HexagonTargetStreamer(S) {
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auto Bits = STI.getFeatureBits();
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unsigned Flags = 0;
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if (Bits[Hexagon::ArchV60])
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Flags = ELF::EF_HEXAGON_MACH_V60;
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else if (Bits[Hexagon::ArchV55])
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Flags = ELF::EF_HEXAGON_MACH_V55;
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else if (Bits[Hexagon::ArchV5])
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Flags = ELF::EF_HEXAGON_MACH_V5;
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else if (Bits[Hexagon::ArchV4])
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Flags = ELF::EF_HEXAGON_MACH_V4;
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getStreamer().getAssembler().setELFHeaderEFlags(Flags);
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}
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void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment,
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unsigned AccessSize) override {
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HexagonMCELFStreamer &HexagonELFStreamer =
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static_cast<HexagonMCELFStreamer &>(getStreamer());
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HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
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AccessSize);
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}
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void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment,
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unsigned AccessSize) override {
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HexagonMCELFStreamer &HexagonELFStreamer =
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static_cast<HexagonMCELFStreamer &>(getStreamer());
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HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
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Symbol, Size, ByteAlignment, AccessSize);
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}
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};
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}
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static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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// VirtualFP = (R30 + #0).
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MCCFIInstruction Inst =
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MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (RM == Reloc::Default)
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RM = Reloc::Static;
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X->initMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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if (SyntaxVariant == 0)
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return (new HexagonInstPrinter(MAI, MII, MRI));
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else
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return nullptr;
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}
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static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool IsVerboseAsm) {
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return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint);
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}
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static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
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MCAsmBackend &MAB, raw_pwrite_stream &OS,
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MCCodeEmitter *Emitter, bool RelaxAll) {
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return createHexagonELFStreamer(Context, MAB, OS, Emitter);
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}
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static MCTargetStreamer *
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createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
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return new HexagonTargetELFStreamer(S, STI);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeHexagonTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
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createHexagonMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
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createHexagonMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
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createHexagonMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
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createHexagonMCSubtargetInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
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createHexagonMCCodeEmitter);
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// Register the asm backend
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TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
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createHexagonAsmBackend);
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// Register the obj streamer
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TargetRegistry::RegisterELFStreamer(TheHexagonTarget, createMCStreamer);
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// Register the asm streamer
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TargetRegistry::RegisterAsmTargetStreamer(TheHexagonTarget,
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createMCAsmTargetStreamer);
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// Register the MC Inst Printer
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TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
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createHexagonMCInstPrinter);
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TargetRegistry::RegisterObjectTargetStreamer(
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TheHexagonTarget, createHexagonObjectTargetStreamer);
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}
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