forked from OSchip/llvm-project
240 lines
8.0 KiB
LLVM
240 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
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define arm_aapcs_vfpcc <2 x i32> @vmulhs_v2i32(<2 x i32> %s0, <2 x i32> %s1) {
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; CHECK-LABEL: vmulhs_v2i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullb.s32 q2, q0, q1
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; CHECK-NEXT: vmov r0, s11
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; CHECK-NEXT: vmov r1, s9
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
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; CHECK-NEXT: asrs r0, r0, #31
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; CHECK-NEXT: asrs r1, r1, #31
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
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; CHECK-NEXT: bx lr
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entry:
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%s0s = sext <2 x i32> %s0 to <2 x i64>
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%s1s = sext <2 x i32> %s1 to <2 x i64>
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%m = mul <2 x i64> %s0s, %s1s
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%s = ashr <2 x i64> %m, <i64 32, i64 32>
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%s2 = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %s2
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}
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define arm_aapcs_vfpcc <2 x i32> @vmulhu_v2i32(<2 x i32> %s0, <2 x i32> %s1) {
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; CHECK-LABEL: vmulhu_v2i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullb.u32 q2, q0, q1
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; CHECK-NEXT: vldr s1, .LCPI1_0
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; CHECK-NEXT: vmov.f32 s0, s9
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; CHECK-NEXT: vmov.f32 s2, s11
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; CHECK-NEXT: vmov.f32 s3, s1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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entry:
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%s0s = zext <2 x i32> %s0 to <2 x i64>
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%s1s = zext <2 x i32> %s1 to <2 x i64>
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%m = mul <2 x i64> %s0s, %s1s
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%s = lshr <2 x i64> %m, <i64 32, i64 32>
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%s2 = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %s2
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}
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define arm_aapcs_vfpcc <4 x i32> @vmulhs_v4i32(<4 x i32> %s0, <4 x i32> %s1) {
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; CHECK-LABEL: vmulhs_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov.f32 s8, s4
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; CHECK-NEXT: vmov.f32 s12, s0
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; CHECK-NEXT: vmov.f32 s10, s5
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; CHECK-NEXT: vmov.f32 s14, s1
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; CHECK-NEXT: vmov r0, s8
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; CHECK-NEXT: vmov r1, s12
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; CHECK-NEXT: vmov.f32 s16, s6
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; CHECK-NEXT: vmov.f32 s18, s7
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; CHECK-NEXT: vmov.f32 s4, s2
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; CHECK-NEXT: vmov.f32 s6, s3
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; CHECK-NEXT: vmullb.s32 q5, q1, q4
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; CHECK-NEXT: smmul r0, r1, r0
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; CHECK-NEXT: vmov r1, s21
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; CHECK-NEXT: vmov q0[2], q0[0], r0, r1
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; CHECK-NEXT: vmov r0, s10
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; CHECK-NEXT: vmov r1, s14
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; CHECK-NEXT: smmul r0, r1, r0
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; CHECK-NEXT: vmov r1, s23
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; CHECK-NEXT: vmov q0[3], q0[1], r0, r1
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: bx lr
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entry:
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%s0s = sext <4 x i32> %s0 to <4 x i64>
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%s1s = sext <4 x i32> %s1 to <4 x i64>
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%m = mul <4 x i64> %s0s, %s1s
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%s = ashr <4 x i64> %m, <i64 32, i64 32, i64 32, i64 32>
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%s2 = trunc <4 x i64> %s to <4 x i32>
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ret <4 x i32> %s2
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}
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define arm_aapcs_vfpcc <4 x i32> @vmulhu_v4i32(<4 x i32> %s0, <4 x i32> %s1) {
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; CHECK-LABEL: vmulhu_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vmov.f32 s12, s6
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; CHECK-NEXT: vmov.f32 s16, s2
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; CHECK-NEXT: vmov.f32 s14, s7
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; CHECK-NEXT: vmov.f32 s18, s3
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; CHECK-NEXT: vmov.f32 s6, s5
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; CHECK-NEXT: vmullb.u32 q2, q4, q3
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; CHECK-NEXT: vmov.f32 s2, s1
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; CHECK-NEXT: vmullb.u32 q3, q0, q1
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; CHECK-NEXT: vmov.f32 s0, s13
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; CHECK-NEXT: vmov.f32 s1, s15
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; CHECK-NEXT: vmov.f32 s2, s9
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; CHECK-NEXT: vmov.f32 s3, s11
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%s0s = zext <4 x i32> %s0 to <4 x i64>
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%s1s = zext <4 x i32> %s1 to <4 x i64>
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%m = mul <4 x i64> %s0s, %s1s
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%s = lshr <4 x i64> %m, <i64 32, i64 32, i64 32, i64 32>
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%s2 = trunc <4 x i64> %s to <4 x i32>
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ret <4 x i32> %s2
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}
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define arm_aapcs_vfpcc <4 x i16> @vmulhs_v4i16(<4 x i16> %s0, <4 x i16> %s1) {
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; CHECK-LABEL: vmulhs_v4i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullb.s16 q0, q0, q1
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; CHECK-NEXT: vshr.s32 q0, q0, #16
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; CHECK-NEXT: bx lr
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entry:
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%s0s = sext <4 x i16> %s0 to <4 x i32>
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%s1s = sext <4 x i16> %s1 to <4 x i32>
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%m = mul <4 x i32> %s0s, %s1s
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%s = ashr <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
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%s2 = trunc <4 x i32> %s to <4 x i16>
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ret <4 x i16> %s2
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}
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define arm_aapcs_vfpcc <4 x i16> @vmulhu_v4i16(<4 x i16> %s0, <4 x i16> %s1) {
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; CHECK-LABEL: vmulhu_v4i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullb.u16 q0, q0, q1
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; CHECK-NEXT: vshr.u32 q0, q0, #16
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; CHECK-NEXT: bx lr
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entry:
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%s0s = zext <4 x i16> %s0 to <4 x i32>
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%s1s = zext <4 x i16> %s1 to <4 x i32>
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%m = mul <4 x i32> %s0s, %s1s
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%s = lshr <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
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%s2 = trunc <4 x i32> %s to <4 x i16>
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ret <4 x i16> %s2
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}
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define arm_aapcs_vfpcc <8 x i16> @vmulhs_v8i16(<8 x i16> %s0, <8 x i16> %s1) {
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; CHECK-LABEL: vmulhs_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullt.s16 q2, q0, q1
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; CHECK-NEXT: vmullb.s16 q0, q0, q1
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; CHECK-NEXT: vshr.u32 q2, q2, #16
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; CHECK-NEXT: vshr.u32 q0, q0, #16
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; CHECK-NEXT: vmovnt.i32 q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%s0s = sext <8 x i16> %s0 to <8 x i32>
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%s1s = sext <8 x i16> %s1 to <8 x i32>
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%m = mul <8 x i32> %s0s, %s1s
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%s = ashr <8 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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%s2 = trunc <8 x i32> %s to <8 x i16>
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ret <8 x i16> %s2
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}
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define arm_aapcs_vfpcc <8 x i16> @vmulhu_v8i16(<8 x i16> %s0, <8 x i16> %s1) {
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; CHECK-LABEL: vmulhu_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullt.u16 q2, q0, q1
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; CHECK-NEXT: vmullb.u16 q0, q0, q1
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; CHECK-NEXT: vshr.u32 q2, q2, #16
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; CHECK-NEXT: vshr.u32 q0, q0, #16
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; CHECK-NEXT: vmovnt.i32 q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%s0s = zext <8 x i16> %s0 to <8 x i32>
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%s1s = zext <8 x i16> %s1 to <8 x i32>
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%m = mul <8 x i32> %s0s, %s1s
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%s = lshr <8 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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%s2 = trunc <8 x i32> %s to <8 x i16>
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ret <8 x i16> %s2
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}
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define arm_aapcs_vfpcc <8 x i8> @vmulhs_v8i8(<8 x i8> %s0, <8 x i8> %s1) {
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; CHECK-LABEL: vmulhs_v8i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullb.s8 q0, q0, q1
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; CHECK-NEXT: vshr.s16 q0, q0, #8
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; CHECK-NEXT: bx lr
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entry:
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%s0s = sext <8 x i8> %s0 to <8 x i16>
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%s1s = sext <8 x i8> %s1 to <8 x i16>
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%m = mul <8 x i16> %s0s, %s1s
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%s = ashr <8 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%s2 = trunc <8 x i16> %s to <8 x i8>
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ret <8 x i8> %s2
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}
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define arm_aapcs_vfpcc <8 x i8> @vmulhu_v8i8(<8 x i8> %s0, <8 x i8> %s1) {
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; CHECK-LABEL: vmulhu_v8i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullb.u8 q0, q0, q1
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; CHECK-NEXT: vshr.u16 q0, q0, #8
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; CHECK-NEXT: bx lr
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entry:
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%s0s = zext <8 x i8> %s0 to <8 x i16>
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%s1s = zext <8 x i8> %s1 to <8 x i16>
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%m = mul <8 x i16> %s0s, %s1s
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%s = lshr <8 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%s2 = trunc <8 x i16> %s to <8 x i8>
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ret <8 x i8> %s2
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}
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define arm_aapcs_vfpcc <16 x i8> @vmulhs_v16i8(<16 x i8> %s0, <16 x i8> %s1) {
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; CHECK-LABEL: vmulhs_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullt.s8 q2, q0, q1
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; CHECK-NEXT: vmullb.s8 q0, q0, q1
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; CHECK-NEXT: vshr.u16 q2, q2, #8
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; CHECK-NEXT: vshr.u16 q0, q0, #8
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; CHECK-NEXT: vmovnt.i16 q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%s0s = sext <16 x i8> %s0 to <16 x i16>
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%s1s = sext <16 x i8> %s1 to <16 x i16>
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%m = mul <16 x i16> %s0s, %s1s
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%s = ashr <16 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%s2 = trunc <16 x i16> %s to <16 x i8>
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ret <16 x i8> %s2
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}
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define arm_aapcs_vfpcc <16 x i8> @vmulhu_v16i8(<16 x i8> %s0, <16 x i8> %s1) {
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; CHECK-LABEL: vmulhu_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmullt.u8 q2, q0, q1
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; CHECK-NEXT: vmullb.u8 q0, q0, q1
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; CHECK-NEXT: vshr.u16 q2, q2, #8
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; CHECK-NEXT: vshr.u16 q0, q0, #8
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; CHECK-NEXT: vmovnt.i16 q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%s0s = zext <16 x i8> %s0 to <16 x i16>
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%s1s = zext <16 x i8> %s1 to <16 x i16>
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%m = mul <16 x i16> %s0s, %s1s
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%s = lshr <16 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%s2 = trunc <16 x i16> %s to <16 x i8>
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ret <16 x i8> %s2
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}
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