forked from OSchip/llvm-project
36 lines
1.5 KiB
LLVM
36 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -frame-pointer=all -mcpu=cortex-a8
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; rdar://8110842
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declare arm_apcscc i32 @__maskrune(i32, i32)
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define arm_apcscc i32 @strncmpic(i8* nocapture %s1, i8* nocapture %s2, i32 %n) nounwind {
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entry:
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br i1 undef, label %bb11, label %bb19
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bb11: ; preds = %entry
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%0 = sext i8 0 to i32 ; <i32> [#uses=1]
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br i1 undef, label %bb.i.i10, label %bb1.i.i11
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bb.i.i10: ; preds = %bb11
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br label %isupper144.exit12
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bb1.i.i11: ; preds = %bb11
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%1 = tail call arm_apcscc i32 @__maskrune(i32 %0, i32 32768) nounwind ; <i32> [#uses=1]
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%2 = icmp ne i32 %1, 0 ; <i1> [#uses=1]
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%3 = zext i1 %2 to i32 ; <i32> [#uses=1]
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%.pre = load i8, i8* undef, align 1 ; <i8> [#uses=1]
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br label %isupper144.exit12
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isupper144.exit12: ; preds = %bb1.i.i11, %bb.i.i10
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%4 = phi i8 [ %.pre, %bb1.i.i11 ], [ 0, %bb.i.i10 ] ; <i8> [#uses=1]
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%5 = phi i32 [ %3, %bb1.i.i11 ], [ undef, %bb.i.i10 ] ; <i32> [#uses=1]
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%6 = icmp eq i32 %5, 0 ; <i1> [#uses=1]
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%7 = sext i8 %4 to i32 ; <i32> [#uses=1]
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%storemerge1 = select i1 %6, i32 %7, i32 undef ; <i32> [#uses=1]
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%8 = sub nsw i32 %storemerge1, 0 ; <i32> [#uses=1]
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ret i32 %8
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bb19: ; preds = %entry
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ret i32 0
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}
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