forked from OSchip/llvm-project
255 lines
6.6 KiB
LLVM
255 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; This test checks that unnecessary masking of shift amount operands is
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; eliminated during instruction selection. The test needs to ensure that the
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; masking is not removed if it may affect the shift amount.
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define i32 @sll_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sll_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sll_redundant_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sllw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = and i32 %b, 31
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%2 = shl i32 %a, %1
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ret i32 %2
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}
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define i32 @sll_non_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sll_non_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 15
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sll_non_redundant_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a1, a1, 15
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; RV64I-NEXT: sllw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = and i32 %b, 15
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%2 = shl i32 %a, %1
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ret i32 %2
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}
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define i32 @srl_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srl_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srl_redundant_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srlw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = and i32 %b, 4095
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%2 = lshr i32 %a, %1
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ret i32 %2
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}
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define i32 @srl_non_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srl_non_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 7
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srl_non_redundant_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a1, a1, 7
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; RV64I-NEXT: srlw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = and i32 %b, 7
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%2 = lshr i32 %a, %1
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ret i32 %2
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}
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define i32 @sra_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sra_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sra_redundant_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = and i32 %b, 65535
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%2 = ashr i32 %a, %1
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ret i32 %2
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}
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define i32 @sra_non_redundant_mask(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sra_non_redundant_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a1, a1, 32
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sra_non_redundant_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraw a0, a0, zero
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; RV64I-NEXT: ret
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%1 = and i32 %b, 32
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%2 = ashr i32 %a, %1
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ret i32 %2
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}
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define i32 @sll_redundant_mask_zeros(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sll_redundant_mask_zeros:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 1
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sll_redundant_mask_zeros:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 1
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; RV64I-NEXT: sllw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i32 %b, 1
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%2 = and i32 %1, 30
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%3 = shl i32 %a, %2
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ret i32 %3
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}
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define i32 @srl_redundant_mask_zeros(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srl_redundant_mask_zeros:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 2
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srl_redundant_mask_zeros:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 2
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; RV64I-NEXT: srlw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i32 %b, 2
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%2 = and i32 %1, 28
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%3 = lshr i32 %a, %2
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ret i32 %3
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}
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define i32 @sra_redundant_mask_zeros(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sra_redundant_mask_zeros:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 3
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sra_redundant_mask_zeros:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 3
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; RV64I-NEXT: sraw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i32 %b, 3
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%2 = and i32 %1, 24
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%3 = ashr i32 %a, %2
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ret i32 %3
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}
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define i64 @sll_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: sll_redundant_mask_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a2, 2
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; RV32I-NEXT: andi a3, a2, 60
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; RV32I-NEXT: addi a4, a3, -32
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; RV32I-NEXT: bltz a4, .LBB9_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sll a1, a0, a4
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB9_2:
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; RV32I-NEXT: sll a1, a1, a2
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; RV32I-NEXT: addi a4, zero, 31
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; RV32I-NEXT: sub a3, a4, a3
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; RV32I-NEXT: srli a4, a0, 1
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; RV32I-NEXT: srl a3, a4, a3
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sll_redundant_mask_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 2
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; RV64I-NEXT: sll a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i64 %b, 2
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%2 = and i64 %1, 60
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%3 = shl i64 %a, %2
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ret i64 %3
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}
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define i64 @srl_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: srl_redundant_mask_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a2, 3
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; RV32I-NEXT: andi a3, a2, 56
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; RV32I-NEXT: addi a4, a3, -32
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; RV32I-NEXT: bltz a4, .LBB10_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srl a0, a1, a4
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB10_2:
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: addi a4, zero, 31
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; RV32I-NEXT: sub a3, a4, a3
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: srl a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: srl_redundant_mask_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 3
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i64 %b, 3
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%2 = and i64 %1, 56
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%3 = lshr i64 %a, %2
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ret i64 %3
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}
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define i64 @sra_redundant_mask_zeros_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: sra_redundant_mask_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a2, 4
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; RV32I-NEXT: andi a3, a2, 48
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; RV32I-NEXT: addi a4, a3, -32
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; RV32I-NEXT: bltz a4, .LBB11_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sra a0, a1, a4
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB11_2:
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: addi a4, zero, 31
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; RV32I-NEXT: sub a3, a4, a3
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: sra a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sra_redundant_mask_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 4
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; RV64I-NEXT: sra a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i64 %b, 4
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%2 = and i64 %1, 48
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%3 = ashr i64 %a, %2
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ret i64 %3
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}
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