forked from OSchip/llvm-project
373 lines
9.2 KiB
LLVM
373 lines
9.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IB
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IBA
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define i64 @slliuw(i64 %a) nounwind {
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; RV64I-LABEL: slliuw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 31
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: slliuw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: slli.uw a0, a0, 1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: slliuw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: slli.uw a0, a0, 1
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; RV64IBA-NEXT: ret
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%conv1 = shl i64 %a, 1
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%shl = and i64 %conv1, 8589934590
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ret i64 %shl
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}
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define i128 @slliuw_2(i32 signext %0, i128* %1) {
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; RV64I-LABEL: slliuw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 28
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; RV64I-NEXT: add a1, a1, a0
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; RV64I-NEXT: ld a0, 0(a1)
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; RV64I-NEXT: ld a1, 8(a1)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: slliuw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: slli.uw a0, a0, 4
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; RV64IB-NEXT: add a1, a1, a0
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; RV64IB-NEXT: ld a0, 0(a1)
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; RV64IB-NEXT: ld a1, 8(a1)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: slliuw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: slli.uw a0, a0, 4
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; RV64IBA-NEXT: add a1, a1, a0
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; RV64IBA-NEXT: ld a0, 0(a1)
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; RV64IBA-NEXT: ld a1, 8(a1)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i128, i128* %1, i64 %3
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%5 = load i128, i128* %4
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ret i128 %5
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}
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define i64 @adduw(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: srli a1, a1, 32
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: add.uw a0, a1, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: add.uw a0, a1, a0
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; RV64IBA-NEXT: ret
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%and = and i64 %b, 4294967295
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%add = add i64 %and, %a
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ret i64 %add
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}
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define signext i8 @adduw_2(i32 signext %0, i8* %1) {
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; RV64I-LABEL: adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lb a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: add.uw a0, a0, a1
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; RV64IB-NEXT: lb a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: add.uw a0, a0, a1
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; RV64IBA-NEXT: lb a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i8, i8* %1, i64 %3
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%5 = load i8, i8* %4
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ret i8 %5
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}
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define i64 @zextw_i64(i64 %a) nounwind {
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; RV64I-LABEL: zextw_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: zextw_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: zext.w a0, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: zextw_i64:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: zext.w a0, a0
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; RV64IBA-NEXT: ret
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%and = and i64 %a, 4294967295
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ret i64 %and
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}
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; This makes sure targetShrinkDemandedConstant changes the and immmediate to
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; allow zext.w or slli+srli.
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define i64 @zextw_demandedbits_i64(i64 %0) {
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; RV64I-LABEL: zextw_demandedbits_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: ori a0, a0, 1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: zextw_demandedbits_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: ori a0, a0, 1
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; RV64IB-NEXT: zext.w a0, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: zextw_demandedbits_i64:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: ori a0, a0, 1
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; RV64IBA-NEXT: zext.w a0, a0
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; RV64IBA-NEXT: ret
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%2 = and i64 %0, 4294967294
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%3 = or i64 %2, 1
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ret i64 %3
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}
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define signext i16 @sh1add(i64 %0, i16* %1) {
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; RV64I-LABEL: sh1add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 1
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lh a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh1add:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh1add a0, a0, a1
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; RV64IB-NEXT: lh a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh1add:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh1add a0, a0, a1
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; RV64IBA-NEXT: lh a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = getelementptr inbounds i16, i16* %1, i64 %0
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%4 = load i16, i16* %3
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ret i16 %4
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}
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define signext i32 @sh2add(i64 %0, i32* %1) {
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; RV64I-LABEL: sh2add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 2
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh2add:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh2add a0, a0, a1
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh2add:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh2add a0, a0, a1
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; RV64IBA-NEXT: lw a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = getelementptr inbounds i32, i32* %1, i64 %0
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%4 = load i32, i32* %3
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ret i32 %4
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}
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define i64 @sh3add(i64 %0, i64* %1) {
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; RV64I-LABEL: sh3add:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 3
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ld a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh3add:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh3add a0, a0, a1
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; RV64IB-NEXT: ld a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh3add:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh3add a0, a0, a1
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; RV64IBA-NEXT: ld a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = getelementptr inbounds i64, i64* %1, i64 %0
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%4 = load i64, i64* %3
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ret i64 %4
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}
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define signext i16 @sh1adduw(i32 signext %0, i16* %1) {
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; RV64I-LABEL: sh1adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 31
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lh a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh1adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh1add.uw a0, a0, a1
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; RV64IB-NEXT: lh a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh1adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh1add.uw a0, a0, a1
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; RV64IBA-NEXT: lh a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i16, i16* %1, i64 %3
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%5 = load i16, i16* %4
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ret i16 %5
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}
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define i64 @sh1adduw_2(i64 %0, i64 %1) {
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; RV64I-LABEL: sh1adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 31
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh1adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh1add.uw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh1adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh1add.uw a0, a0, a1
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; RV64IBA-NEXT: ret
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%3 = shl i64 %0, 1
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%4 = and i64 %3, 8589934590
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%5 = add i64 %4, %1
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ret i64 %5
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}
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define signext i32 @sh2adduw(i32 signext %0, i32* %1) {
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; RV64I-LABEL: sh2adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 30
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh2adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh2add.uw a0, a0, a1
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; RV64IB-NEXT: lw a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh2adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh2add.uw a0, a0, a1
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; RV64IBA-NEXT: lw a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i32, i32* %1, i64 %3
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%5 = load i32, i32* %4
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ret i32 %5
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}
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define i64 @sh2adduw_2(i64 %0, i64 %1) {
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; RV64I-LABEL: sh2adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 30
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh2adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh2add.uw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh2adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh2add.uw a0, a0, a1
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; RV64IBA-NEXT: ret
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%3 = shl i64 %0, 2
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%4 = and i64 %3, 17179869180
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%5 = add i64 %4, %1
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ret i64 %5
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}
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define i64 @sh3adduw(i32 signext %0, i64* %1) {
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; RV64I-LABEL: sh3adduw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 29
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: ld a0, 0(a0)
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh3adduw:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh3add.uw a0, a0, a1
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; RV64IB-NEXT: ld a0, 0(a0)
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh3adduw:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh3add.uw a0, a0, a1
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; RV64IBA-NEXT: ld a0, 0(a0)
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; RV64IBA-NEXT: ret
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%3 = zext i32 %0 to i64
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%4 = getelementptr inbounds i64, i64* %1, i64 %3
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%5 = load i64, i64* %4
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ret i64 %5
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}
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define i64 @sh3adduw_2(i64 %0, i64 %1) {
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; RV64I-LABEL: sh3adduw_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 29
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sh3adduw_2:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sh3add.uw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBA-LABEL: sh3adduw_2:
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; RV64IBA: # %bb.0:
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; RV64IBA-NEXT: sh3add.uw a0, a0, a1
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; RV64IBA-NEXT: ret
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%3 = shl i64 %0, 3
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%4 = and i64 %3, 34359738360
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%5 = add i64 %4, %1
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ret i64 %5
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}
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