forked from OSchip/llvm-project
192 lines
5.2 KiB
LLVM
192 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
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declare half @llvm.sqrt.f16(half)
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define half @sqrt_f16(half %a) nounwind {
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; RV32IZFH-LABEL: sqrt_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsqrt.h fa0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: sqrt_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fsqrt.h fa0, fa0
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: sqrt_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsqrt.h fa0, fa0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: sqrt_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fsqrt.h fa0, fa0
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.sqrt.f16(half %a)
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ret half %1
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}
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declare half @llvm.fma.f16(half, half, half)
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define half @fma_f16(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fma_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: fma_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fma_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fma_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
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ret half %1
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}
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declare half @llvm.fmuladd.f16(half, half, half)
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define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fmuladd_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: fmuladd_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmuladd_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fmuladd_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
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ret half %1
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}
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declare half @llvm.fabs.f16(half)
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define half @fabs_f16(half %a) nounwind {
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; RV32IZFH-LABEL: fabs_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fabs.h fa0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: fabs_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fabs.h fa0, fa0
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fabs_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fabs.h fa0, fa0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fabs_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fabs.h fa0, fa0
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.fabs.f16(half %a)
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ret half %1
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}
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declare half @llvm.minnum.f16(half, half)
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define half @minnum_f16(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: minnum_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: minnum_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fmin.h fa0, fa0, fa1
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: minnum_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: minnum_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fmin.h fa0, fa0, fa1
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.minnum.f16(half %a, half %b)
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ret half %1
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}
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declare half @llvm.maxnum.f16(half, half)
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define half @maxnum_f16(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: maxnum_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: maxnum_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fmax.h fa0, fa0, fa1
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: maxnum_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: maxnum_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fmax.h fa0, fa0, fa1
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.maxnum.f16(half %a, half %b)
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ret half %1
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}
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declare half @llvm.copysign.f16(half, half)
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define half @copysign_f16(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: copysign_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV32IDZFH-LABEL: copysign_f16:
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; RV32IDZFH: # %bb.0:
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; RV32IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
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; RV32IDZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: copysign_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: copysign_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
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; RV64IDZFH-NEXT: ret
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%1 = call half @llvm.copysign.f16(half %a, half %b)
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ret half %1
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}
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