| .. |
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GlobalISel
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…
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intrinsics
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…
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rvv
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[RISCV][NFC] Simplify test run lines
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2021-05-13 12:41:00 +01:00 |
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add-before-shl.ll
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…
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add-imm.ll
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[RISCV] Optimize addition with immediate
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2021-04-26 13:26:17 +08:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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…
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addimm-mulimm.ll
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[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
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2020-07-10 18:33:12 -07:00 |
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addrspacecast.ll
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[RISCV] Assume no-op addrspacecasts by default
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2020-12-18 21:03:37 +00:00 |
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align.ll
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…
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alloca.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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alu8.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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alu16.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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alu32.ll
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[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff).
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2021-03-25 09:03:25 -07:00 |
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alu64.ll
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[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
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2020-11-25 21:57:48 -08:00 |
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analyze-branch.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-flag.ll
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…
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atomic-cmpxchg.ll
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[RISCV] Copy isUnneededShiftMask from X86.
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2021-01-27 20:46:10 -08:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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atomic-rmw.ll
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[RISCV] Copy isUnneededShiftMask from X86.
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2021-01-27 20:46:10 -08:00 |
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atomic-signext.ll
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Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"
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2021-05-12 09:46:18 -05:00 |
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attributes.ll
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[RISCV] Update the version number to v0.10 for vector.
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2021-01-30 07:20:05 +08:00 |
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blockaddress.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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branch-relaxation.ll
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[RISCV] Indirect branch generation in position independent code
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2020-08-17 13:09:26 +01:00 |
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branch.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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bswap-ctlz-cttz-ctpop.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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byval.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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callee-saved-fpr32s.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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callee-saved-fpr64s.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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callee-saved-gprs.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-half.ll
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[RISCV] Improve 64-bit integer constant materialization for more cases.
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2021-04-02 10:18:08 -07:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32d.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-sext-zext.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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calls.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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cmp-bool.ll
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[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
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2020-07-15 07:34:22 +00:00 |
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codemodel-lowering.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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compress-float.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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compress-inline-asm.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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compress.ll
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[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
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2020-12-04 10:34:12 -08:00 |
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copy-frameindex.mir
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[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
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2020-11-03 03:55:47 +00:00 |
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copysign-casts.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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disable-tail-calls.ll
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…
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disjoint.ll
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…
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div.ll
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[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
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2021-04-11 13:59:51 -07:00 |
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double-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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double-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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double-calling-conv.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-convert.ll
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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.
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2021-04-22 15:18:15 -07:00 |
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double-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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double-frem.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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double-intrinsics.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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double-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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double-mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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double-previous-failure.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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double-stack-spill-restore.ll
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[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
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2021-01-25 16:37:21 -08:00 |
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dwarf-eh.ll
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…
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elf-preemption.ll
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[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
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2021-05-11 11:29:45 -07:00 |
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exception-pointer-register.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fastcc-float.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fastcc-int.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fixups-diff.ll
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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fixups-relax-diff.ll
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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float-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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float-bit-preserving-dagcombines.ll
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[RISCV] Improve 64-bit integer materialization for some cases.
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2021-04-01 09:12:52 -07:00 |
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float-bitmanip-dagcombines.ll
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…
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float-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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float-convert.ll
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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.
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2021-04-22 15:18:15 -07:00 |
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float-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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float-frem.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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float-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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float-intrinsics.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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float-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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float-mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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float-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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flt-rounds.ll
|
…
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fold-addi-loadstore.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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fp-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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fp16-promote.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
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2021-04-01 12:41:57 -07:00 |
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fp128.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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fpenv.ll
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[RISCV] Custom lowering of SET_ROUNDING
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2021-04-22 15:04:55 +07:00 |
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frame-info.ll
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[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
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2021-01-15 11:14:14 -08:00 |
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frame.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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frameaddr-returnaddr.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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get-register-invalid.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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get-register-noreserve.ll
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…
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get-register-reserve.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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get-setcc-result-type.ll
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…
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ghccc-rv32.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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ghccc-rv64.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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half-arith.ll
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[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
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2020-12-02 21:13:42 -08:00 |
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half-bitmanip-dagcombines.ll
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[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
|
2021-04-01 12:41:57 -07:00 |
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half-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
|
2021-01-19 11:21:48 -08:00 |
|
half-convert.ll
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[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.
|
2021-04-22 15:18:15 -07:00 |
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half-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
|
2021-01-12 10:45:03 -08:00 |
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half-imm.ll
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[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
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half-intrinsics.ll
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[RISCV] Add f16 to isFMAFasterThanFMulAndFAdd now that the Zfh extension is supported
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2020-12-02 20:31:43 -08:00 |
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half-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
|
2020-12-10 09:15:52 -08:00 |
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half-mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
half-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
|
2021-01-14 13:41:40 -08:00 |
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hoist-global-addr-base.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
|
2021-03-15 11:32:43 -07:00 |
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i32-icmp.ll
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[RISCV] Optimize seteq/setne pattern expansions for better code size
|
2020-02-11 22:45:15 +08:00 |
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imm-cse.ll
|
…
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|
|
imm.ll
|
[RISCV] Improve 64-bit integer constant materialization for more cases.
|
2021-04-02 10:18:08 -07:00 |
|
indirectbr.ll
|
[RISCV] Fix inaccurate annotations on PseudoBRIND
|
2020-08-21 11:38:42 +01:00 |
|
init-array.ll
|
…
|
|
|
inline-asm-abi-names.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
inline-asm-clobbers.ll
|
…
|
|
|
inline-asm-d-abi-names.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
inline-asm-d-constraint-f.ll
|
…
|
|
|
inline-asm-f-abi-names.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
inline-asm-f-constraint-f.ll
|
…
|
|
|
inline-asm-i-constraint-i1.ll
|
…
|
|
|
inline-asm-invalid.ll
|
…
|
|
|
inline-asm.ll
|
[MC][RISCV] Set UseIntegratedAssembler to true
|
2020-07-12 21:04:48 -07:00 |
|
interrupt-attr-args-error.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
interrupt-attr-callee.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
interrupt-attr-invalid.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
interrupt-attr-nocall.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
interrupt-attr-ret-error.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
interrupt-attr.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
jumptable.ll
|
[RISCV] Basic jump table lowering
|
2020-12-22 15:05:54 +00:00 |
|
large-stack.ll
|
[RISCV] remove redundant instruction when eliminate frame index
|
2021-03-21 18:54:00 +08:00 |
|
legalize-fneg.ll
|
…
|
|
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lit.local.cfg
|
…
|
|
|
lsr-legaladdimm.ll
|
…
|
|
|
machineoutliner.mir
|
[RISCV] Enable the machine outliner for RISC-V
|
2019-12-19 16:41:53 +00:00 |
|
mattr-invalid-combination.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
mem.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
mem64.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
mir-target-flags.ll
|
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
|
2020-12-05 14:54:37 -08:00 |
|
module-target-abi.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
module-target-abi2.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
mul.ll
|
[RISCV] Add custom type legalization to form MULHSU when possible.
|
2021-04-01 10:15:55 -07:00 |
|
musttail-call.ll
|
OpaquePtr: Bulk update tests to use typed sret
|
2020-11-20 17:58:26 -05:00 |
|
neg-abs.ll
|
[RISCV][NFC] Increase test coverage of Zbt extension
|
2021-01-18 17:30:35 +00:00 |
|
nomerge.ll
|
Add NoMerge MIFlag to avoid MIR branch folding
|
2020-05-29 12:31:06 -07:00 |
|
option-nopic.ll
|
[RISCV][AsmParser] Implement .option (no)pic
|
2020-04-17 12:08:30 +00:00 |
|
option-norelax.ll
|
[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
|
2020-03-05 18:05:28 -08:00 |
|
option-norvc.ll
|
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
|
option-pic.ll
|
[RISCV][AsmParser] Implement .option (no)pic
|
2020-04-17 12:08:30 +00:00 |
|
option-relax.ll
|
[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
|
2020-03-05 18:05:28 -08:00 |
|
option-rvc.ll
|
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
|
out-of-reach-emergency-slot.mir
|
[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
|
2021-01-23 09:10:03 +00:00 |
|
patchable-function-entry.ll
|
[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
|
2021-03-16 10:02:35 -07:00 |
|
pic-models.ll
|
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
|
2020-07-14 11:15:01 +01:00 |
|
pr40333.ll
|
…
|
|
|
prefetch.ll
|
…
|
|
|
readcyclecounter.ll
|
…
|
|
|
rem.ll
|
[RISCV] Add i8/i16 test cases to div.ll and i8/i16/i64 to rem.ll. NFC
|
2021-02-04 16:46:23 -08:00 |
|
remat.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
reserved-reg-errors.ll
|
…
|
|
|
reserved-regs.ll
|
…
|
|
|
rotl-rotr.ll
|
…
|
|
|
rv32e.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
rv32i-rv64i-float-double.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv32i-rv64i-half.ll
|
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
|
2021-04-01 12:41:57 -07:00 |
|
rv32zba.ll
|
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
|
2021-03-22 19:17:04 -07:00 |
|
rv32zbb-intrinsic.ll
|
Recommit "[RISCV] Add IR intrinsic for Zbb extension"
|
2021-04-02 11:50:19 -07:00 |
|
rv32zbb-zbp.ll
|
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
|
2021-04-29 09:43:51 -07:00 |
|
rv32zbb.ll
|
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
|
2021-03-22 19:17:04 -07:00 |
|
rv32zbc-intrinsic.ll
|
[RISCV] Add IR intrinsics for Zbc extension
|
2021-04-02 12:09:13 -07:00 |
|
rv32zbe-intrinsic.ll
|
[RISCV] [1/2] Add IR intrinsic for Zbe extension
|
2021-04-25 19:14:34 -07:00 |
|
rv32zbp-intrinsic.ll
|
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
|
2021-04-25 21:54:06 -07:00 |
|
rv32zbp.ll
|
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
|
2021-03-22 19:17:04 -07:00 |
|
rv32zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv32zbs.ll
|
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
|
2021-04-29 09:43:51 -07:00 |
|
rv32zbt.ll
|
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
|
2021-04-29 09:43:51 -07:00 |
|
rv64-large-stack.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64d-double-convert.ll
|
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
|
2020-12-04 18:40:02 -08:00 |
|
rv64f-float-convert.ll
|
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
|
2020-12-04 18:40:02 -08:00 |
|
rv64f-half-convert.ll
|
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
|
2020-12-04 18:40:02 -08:00 |
|
rv64i-complex-float.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64i-demanded-bits.ll
|
[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
|
2020-10-29 14:52:53 -07:00 |
|
rv64i-double-softfloat.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64i-exhaustive-w-insts.ll
|
[RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3.
|
2021-03-25 23:31:01 -07:00 |
|
rv64i-single-softfloat.ll
|
[RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.
|
2021-01-25 09:33:48 -08:00 |
|
rv64i-tricky-shifts.ll
|
…
|
|
|
rv64i-w-insts-legalization.ll
|
[RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64
|
2021-03-20 14:55:46 -07:00 |
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.
|
2021-02-22 14:56:22 -08:00 |
|
rv64m-w-insts-legalization.ll
|
Revert "[BPI] Improve static heuristics for integer comparisons"
|
2020-08-17 20:44:33 +02:00 |
|
rv64zba.ll
|
[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff).
|
2021-03-25 09:03:25 -07:00 |
|
rv64zbb-intrinsic.ll
|
[RISCV] Use gorciw for i32 orc.b intrinsic when Zbp is enabled.
|
2021-04-04 17:14:28 -07:00 |
|
rv64zbb-zbp.ll
|
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
|
2021-04-11 13:59:51 -07:00 |
|
rv64zbb.ll
|
[RISCV] Add RISCVISD opcodes for CLZW and CTZW.
|
2021-03-31 09:40:07 -07:00 |
|
rv64zbc-intrinsic.ll
|
[RISCV] Add IR intrinsics for Zbc extension
|
2021-04-02 12:09:13 -07:00 |
|
rv64zbe-intrinsic.ll
|
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
|
2021-04-25 21:54:06 -07:00 |
|
rv64zbp-intrinsic.ll
|
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
|
2021-04-25 21:54:06 -07:00 |
|
rv64zbp.ll
|
[RISCV] Improve 64-bit integer materialization for some cases.
|
2021-04-01 09:12:52 -07:00 |
|
rv64zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv64zbs.ll
|
[RISCV] Improve 64-bit integer materialization for some cases.
|
2021-04-01 09:12:52 -07:00 |
|
rv64zbt.ll
|
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
|
2021-03-22 19:17:04 -07:00 |
|
sadd_sat.ll
|
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
|
2021-04-07 13:47:17 -07:00 |
|
sadd_sat_plus.ll
|
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
|
2021-04-07 13:47:17 -07:00 |
|
saverestore.ll
|
[RISCV] Don't emit save-restore call if function is a interrupt handler
|
2021-04-16 12:54:47 +08:00 |
|
scalable-vector-struct.ll
|
[RISCV] Use whole register load/store for generic load/store.
|
2021-02-09 15:52:04 +08:00 |
|
sdata-limit-0.ll
|
…
|
|
|
sdata-limit-4.ll
|
…
|
|
|
sdata-limit-8.ll
|
…
|
|
|
sdata-local-sym.ll
|
…
|
|
|
select-and.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-bare.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-binop-identity.ll
|
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
|
2021-04-29 09:43:51 -07:00 |
|
select-cc.ll
|
[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.
|
2021-03-12 11:50:10 -08:00 |
|
select-const.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-optimize-multiple.ll
|
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
|
2021-01-22 14:51:22 -08:00 |
|
select-optimize-multiple.mir
|
[RISCV][NFC] Increase test coverage of Zbt extension
|
2021-01-18 17:30:35 +00:00 |
|
select-or.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
setcc-logic.ll
|
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
|
2021-01-25 16:37:21 -08:00 |
|
sext-zext-trunc.ll
|
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
|
2021-01-25 16:37:21 -08:00 |
|
shadowcallstack.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
shift-masked-shamt.ll
|
[RISCV] Copy isUnneededShiftMask from X86.
|
2021-01-27 20:46:10 -08:00 |
|
shifts.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
shrinkwrap.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
spill-fpr-scalar.ll
|
[RISCV] Spilling for RISC-V V extension. (2nd version)
|
2021-02-17 14:05:19 +08:00 |
|
split-offsets.ll
|
…
|
|
|
split-sp-adjust.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
srem-lkk.ll
|
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
|
2021-02-11 09:43:13 -08:00 |
|
srem-seteq-illegal-types.ll
|
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.
|
2021-05-11 09:42:48 -07:00 |
|
srem-vector-lkk.ll
|
[RISCV] Improve 64-bit integer materialization for some cases.
|
2021-04-01 09:12:52 -07:00 |
|
ssub_sat.ll
|
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
|
2021-04-07 13:47:17 -07:00 |
|
ssub_sat_plus.ll
|
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
|
2021-04-07 13:47:17 -07:00 |
|
stack-realignment-with-variable-sized-objects.ll
|
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
|
2021-01-15 11:14:14 -08:00 |
|
stack-realignment.ll
|
[RISCV] remove redundant instruction when eliminate frame index
|
2021-03-21 18:54:00 +08:00 |
|
stack-slot-size.ll
|
[RISCV] Fix stack slot for argument types (Bug 49500)
|
2021-04-29 09:10:48 +01:00 |
|
stack-store-check.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
subtarget-features-std-ext.ll
|
[RISCV] Support ABI checking with per function target-features
|
2020-01-22 08:12:28 -08:00 |
|
tail-calls.ll
|
OpaquePtr: Bulk update tests to use typed sret
|
2020-11-20 17:58:26 -05:00 |
|
target-abi-invalid.ll
|
…
|
|
|
target-abi-valid.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
thread-pointer.ll
|
[RISCV] Support llvm.thread.pointer
|
2020-03-27 17:30:12 -07:00 |
|
tls-models.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
uadd_sat.ll
|
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
|
2021-03-16 07:44:06 -07:00 |
|
uadd_sat_plus.ll
|
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
|
2021-03-16 07:44:06 -07:00 |
|
umulo-128-legalisation-lowering.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
urem-lkk.ll
|
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
|
2021-02-11 09:43:13 -08:00 |
|
urem-seteq-illegal-types.ll
|
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.
|
2021-05-11 09:42:48 -07:00 |
|
urem-vector-lkk.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
usub_sat.ll
|
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
|
2021-03-16 07:44:06 -07:00 |
|
usub_sat_plus.ll
|
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
|
2021-03-16 07:44:06 -07:00 |
|
vararg.ll
|
[RISCV] remove redundant instruction when eliminate frame index
|
2021-03-21 18:54:00 +08:00 |
|
vec3-setcc-crash.ll
|
[RISCV] Fix a codegen crash in getSetCCResultType
|
2021-01-27 10:22:54 +00:00 |
|
vector-abi.ll
|
[RISCV] Fix stack slot for argument types (Bug 49500)
|
2021-04-29 09:10:48 +01:00 |
|
verify-instr.mir
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
wide-mem.ll
|
[RISCV] Fold ADDIs into load/stores with nonzero offsets
|
2020-07-06 17:32:57 +01:00 |
|
xaluo.ll
|
[RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation
|
2021-03-27 15:37:18 -07:00 |
|
zext-with-load-is-free.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
zfh-imm.ll
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
797e580db9