forked from OSchip/llvm-project
319 lines
14 KiB
LLVM
319 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -expand-reductions -S | FileCheck %s
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; Tests without a target which should expand all reductions
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declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.mul.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
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declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
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declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
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declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
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declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
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declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
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declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
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declare i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8>)
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define i64 @add_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @add_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[BIN_RDX]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @mul_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @mul_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = mul <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[BIN_RDX]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.mul.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @and_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @and_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = and <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[BIN_RDX]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @or_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @or_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[BIN_RDX]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @xor_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @xor_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = xor <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[BIN_RDX]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define float @fadd_f32(<4 x float> %vec) {
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; CHECK-LABEL: @fadd_f32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fadd fast float 0.000000e+00, [[TMP0]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.0, <4 x float> %vec)
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ret float %r
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}
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define float @fadd_f32_accum(float %accum, <4 x float> %vec) {
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; CHECK-LABEL: @fadd_f32_accum(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fadd fast float [[ACCUM:%.*]], [[TMP0]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %accum, <4 x float> %vec)
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ret float %r
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}
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define float @fadd_f32_strict(<4 x float> %vec) {
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; CHECK-LABEL: @fadd_f32_strict(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[VEC:%.*]], i32 0
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd float undef, [[TMP0]]
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[VEC]], i32 1
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; CHECK-NEXT: [[BIN_RDX1:%.*]] = fadd float [[BIN_RDX]], [[TMP1]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[VEC]], i32 2
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd float [[BIN_RDX1]], [[TMP2]]
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[VEC]], i32 3
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fadd float [[BIN_RDX2]], [[TMP3]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call float @llvm.vector.reduce.fadd.f32.v4f32(float undef, <4 x float> %vec)
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ret float %r
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}
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define float @fadd_f32_strict_accum(float %accum, <4 x float> %vec) {
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; CHECK-LABEL: @fadd_f32_strict_accum(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[VEC:%.*]], i32 0
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd float [[ACCUM:%.*]], [[TMP0]]
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[VEC]], i32 1
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; CHECK-NEXT: [[BIN_RDX1:%.*]] = fadd float [[BIN_RDX]], [[TMP1]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[VEC]], i32 2
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fadd float [[BIN_RDX1]], [[TMP2]]
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[VEC]], i32 3
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fadd float [[BIN_RDX2]], [[TMP3]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call float @llvm.vector.reduce.fadd.f32.v4f32(float %accum, <4 x float> %vec)
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ret float %r
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}
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define float @fmul_f32(<4 x float> %vec) {
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; CHECK-LABEL: @fmul_f32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul fast <4 x float> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fmul fast float 1.000000e+00, [[TMP0]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %vec)
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ret float %r
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}
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define float @fmul_f32_accum(float %accum, <4 x float> %vec) {
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; CHECK-LABEL: @fmul_f32_accum(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[VEC:%.*]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul fast <4 x float> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul fast <4 x float> [[BIN_RDX]], [[RDX_SHUF1]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[BIN_RDX2]], i32 0
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fmul fast float [[ACCUM:%.*]], [[TMP0]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %accum, <4 x float> %vec)
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ret float %r
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}
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define float @fmul_f32_strict(<4 x float> %vec) {
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; CHECK-LABEL: @fmul_f32_strict(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[VEC:%.*]], i32 0
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul float undef, [[TMP0]]
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[VEC]], i32 1
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; CHECK-NEXT: [[BIN_RDX1:%.*]] = fmul float [[BIN_RDX]], [[TMP1]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[VEC]], i32 2
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul float [[BIN_RDX1]], [[TMP2]]
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[VEC]], i32 3
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fmul float [[BIN_RDX2]], [[TMP3]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call float @llvm.vector.reduce.fmul.f32.v4f32(float undef, <4 x float> %vec)
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ret float %r
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}
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define float @fmul_f32_strict_accum(float %accum, <4 x float> %vec) {
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; CHECK-LABEL: @fmul_f32_strict_accum(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[VEC:%.*]], i32 0
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; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul float [[ACCUM:%.*]], [[TMP0]]
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[VEC]], i32 1
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; CHECK-NEXT: [[BIN_RDX1:%.*]] = fmul float [[BIN_RDX]], [[TMP1]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[VEC]], i32 2
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; CHECK-NEXT: [[BIN_RDX2:%.*]] = fmul float [[BIN_RDX1]], [[TMP2]]
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[VEC]], i32 3
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; CHECK-NEXT: [[BIN_RDX3:%.*]] = fmul float [[BIN_RDX2]], [[TMP3]]
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; CHECK-NEXT: ret float [[BIN_RDX3]]
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;
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entry:
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%r = call float @llvm.vector.reduce.fmul.f32.v4f32(float %accum, <4 x float> %vec)
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ret float %r
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}
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define i64 @smax_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @smax_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = icmp sgt <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select <2 x i1> [[RDX_MINMAX_CMP]], <2 x i64> [[VEC]], <2 x i64> [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[RDX_MINMAX_SELECT]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @smin_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @smin_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = icmp slt <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select <2 x i1> [[RDX_MINMAX_CMP]], <2 x i64> [[VEC]], <2 x i64> [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[RDX_MINMAX_SELECT]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @umax_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @umax_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = icmp ugt <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select <2 x i1> [[RDX_MINMAX_CMP]], <2 x i64> [[VEC]], <2 x i64> [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[RDX_MINMAX_SELECT]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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define i64 @umin_i64(<2 x i64> %vec) {
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; CHECK-LABEL: @umin_i64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> poison, <2 x i32> <i32 1, i32 undef>
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; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = icmp ult <2 x i64> [[VEC]], [[RDX_SHUF]]
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; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select <2 x i1> [[RDX_MINMAX_CMP]], <2 x i64> [[VEC]], <2 x i64> [[RDX_SHUF]]
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; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[RDX_MINMAX_SELECT]], i32 0
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; CHECK-NEXT: ret i64 [[TMP0]]
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;
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entry:
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%r = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec)
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ret i64 %r
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}
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; FIXME: Expand using maxnum intrinsic?
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define double @fmax_f64(<2 x double> %vec) {
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; CHECK-LABEL: @fmax_f64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[R:%.*]] = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> [[VEC:%.*]])
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; CHECK-NEXT: ret double [[R]]
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;
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entry:
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%r = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %vec)
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ret double %r
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}
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; FIXME: Expand using minnum intrinsic?
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define double @fmin_f64(<2 x double> %vec) {
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; CHECK-LABEL: @fmin_f64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[R:%.*]] = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> [[VEC:%.*]])
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; CHECK-NEXT: ret double [[R]]
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;
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entry:
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%r = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %vec)
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ret double %r
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}
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; FIXME: Why is this not expanded?
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; Test when the vector size is not power of two.
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define i8 @test_v3i8(<3 x i8> %a) nounwind {
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; CHECK-LABEL: @test_v3i8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[B:%.*]] = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> [[A:%.*]])
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; CHECK-NEXT: ret i8 [[B]]
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;
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entry:
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%b = call i8 @llvm.vector.reduce.and.i8.v3i8(<3 x i8> %a)
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ret i8 %b
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}
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