forked from OSchip/llvm-project
168 lines
5.0 KiB
YAML
168 lines
5.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \
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# RUN: %s -o - | FileCheck %s
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--- |
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define void @dont_outline_asm() #0 { ret void }
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define void @dont_outline_lr() #0 { ret void }
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define void @dont_outline_lr2() #0 { ret void }
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define void @dont_outline_it() #0 { ret void }
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define void @dont_outline_pic() #0 { ret void }
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define void @dont_outline_mve() #0 { ret void }
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declare void @z(i32, i32, i32, i32)
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attributes #0 = { minsize optsize }
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...
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---
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name: dont_outline_asm
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_asm
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; CHECK: bb.0:
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; CHECK: INLINEASM &"movs r0, #42", 1
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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; CHECK: bb.1:
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; CHECK: INLINEASM &"movs r0, #42", 1
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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bb.0:
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INLINEASM &"movs r0, #42", 1
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$r0, dead $cpsr = tMOVi8 1, 14, $noreg
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$r1, dead $cpsr = tMOVi8 1, 14, $noreg
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$r2, dead $cpsr = tMOVi8 1, 14, $noreg
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$r3, dead $cpsr = tMOVi8 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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INLINEASM &"movs r0, #42", 1
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$r0, dead $cpsr = tMOVi8 1, 14, $noreg
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$r1, dead $cpsr = tMOVi8 1, 14, $noreg
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$r2, dead $cpsr = tMOVi8 1, 14, $noreg
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$r3, dead $cpsr = tMOVi8 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_lr
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_lr
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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liveins: $lr
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$r0 = tMOVr $lr, 14, $noreg
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$r1 = tMOVr $lr, 14, $noreg
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$r2 = tMOVr $lr, 14, $noreg
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$r3 = tMOVr $lr, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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liveins: $lr
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$r0 = tMOVr $lr, 14, $noreg
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$r1 = tMOVr $lr, 14, $noreg
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$r2 = tMOVr $lr, 14, $noreg
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$r3 = tMOVr $lr, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_lr2
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_lr2
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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liveins: $r0
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$lr = tMOVr $r0, 14, $noreg
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$r1 = tMOVr $r0, 14, $noreg
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$r2 = tMOVr $r0, 14, $noreg
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$r3 = tMOVr $r0, 14, $noreg
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$r4 = tMOVr $r0, 14, $noreg
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tBLXr 14, $lr, $noreg
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bb.1:
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liveins: $r0
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$lr = tMOVr $r0, 14, $noreg
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$r1 = tMOVr $r0, 14, $noreg
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$r2 = tMOVr $r0, 14, $noreg
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$r3 = tMOVr $r0, 14, $noreg
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$r4 = tMOVr $r0, 14, $noreg
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tBLXr 14, $lr, $noreg
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_it
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_it
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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t2IT 0, 1, implicit-def $itstate
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$r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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tBL 14, $noreg, @z
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bb.1:
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t2IT 0, 1, implicit-def $itstate
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$r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_pic
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_pic
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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$r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = PICADD $r0, 1, 14, $noreg
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$r1 = PICLDR $r0, 2, 14, $noreg
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PICSTR $r0, $r1, 3, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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$r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = PICADD $r0, 1, 14, $noreg
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$r1 = PICLDR $r0, 2, 14, $noreg
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PICSTR $r0, $r1, 3, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_mve
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_mve
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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liveins: $r3, $r4, $q0, $q3, $q4, $q5
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$q5 = MVE_VDUP32 $r3, 0, $noreg, $q5
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$q4 = MVE_VDUP32 $r4, 0, $noreg, $q4
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$q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0
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$lr = t2DoLoopStart $r4
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$r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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liveins: $r3, $r4, $q0, $q3, $q4, $q5
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$q5 = MVE_VDUP32 $r3, 0, $noreg, $q5
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$q4 = MVE_VDUP32 $r4, 0, $noreg, $q4
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$q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0
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$lr = t2DoLoopStart $r4
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$r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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