forked from OSchip/llvm-project
24261729a4
This adds a generic opcode which communicates that a type has already been
zero-extended from a narrower type.
This is intended to be similar to AssertZext in SelectionDAG.
For example,
```
%x_was_extended:_(s64) = G_ASSERT_ZEXT %x, 16
```
Signifies that the top 48 bits of %x are known to be 0.
This is useful in cases like this:
```
define i1 @zeroext_param(i8 zeroext %x) {
%cmp = icmp ult i8 %x, -20
ret i1 %cmp
}
```
In AArch64, `%x` must use a 32-bit register, which is then truncated to a 8-bit
value.
If we know that `%x` is already zero-ed out in the relevant high bits, we can
avoid the truncate.
Currently, in GISel, this looks like this:
```
_zeroext_param:
and w8, w0, #0xff ; We don't actually need this!
cmp w8, #236
cset w0, lo
ret
```
While SDAG does not produce the truncation, since it knows that it's
unnecessary:
```
_zeroext_param:
cmp w0, #236
cset w0, lo
ret
```
This patch
- Adds G_ASSERT_ZEXT
- Adds MIRBuilder support for it
- Adds MachineVerifier support for it
- Documents it
It also puts G_ASSERT_ZEXT into its own class of "hint instruction." (There
should be a G_ASSERT_SEXT in the future, maybe a G_ASSERT_ALIGN as well.)
This allows us to skip over hints in the legalizer etc. These can then later
be selected like COPY instructions or removed.
Differential Revision: https://reviews.llvm.org/D95564
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| .. | ||
| generic-vreg-undef-use.mir | ||
| live-ins-01.mir | ||
| live-ins-02.mir | ||
| live-ins-03.mir | ||
| test_copy.mir | ||
| test_copy_mismatch_types.mir | ||
| test_g_add.mir | ||
| test_g_addrspacecast.mir | ||
| test_g_assert_zext.mir | ||
| test_g_assert_zext_register_bank_class.mir | ||
| test_g_bitcast.mir | ||
| test_g_brindirect_is_indirect_branch.mir | ||
| test_g_brjt.mir | ||
| test_g_brjt_is_indirect_branch.mir | ||
| test_g_build_vector.mir | ||
| test_g_build_vector_trunc.mir | ||
| test_g_concat_vectors.mir | ||
| test_g_constant.mir | ||
| test_g_dyn_stackalloc.mir | ||
| test_g_extract.mir | ||
| test_g_fcmp.mir | ||
| test_g_fconstant.mir | ||
| test_g_icmp.mir | ||
| test_g_insert.mir | ||
| test_g_intrinsic.mir | ||
| test_g_intrinsic_w_side_effects.mir | ||
| test_g_inttoptr.mir | ||
| test_g_jump_table.mir | ||
| test_g_load.mir | ||
| test_g_memcpy.mir | ||
| test_g_memset.mir | ||
| test_g_merge_values.mir | ||
| test_g_phi.mir | ||
| test_g_ptr_add.mir | ||
| test_g_ptrmask.mir | ||
| test_g_ptrtoint.mir | ||
| test_g_select.mir | ||
| test_g_sext_inreg.mir | ||
| test_g_sextload.mir | ||
| test_g_shuffle_vector.mir | ||
| test_g_store.mir | ||
| test_g_trunc.mir | ||
| test_g_zextload.mir | ||
| test_phis_precede_nonphis.mir | ||
| test_vector_reductions.mir | ||
| verifier-generic-extend-truncate.mir | ||
| verifier-generic-types-1.mir | ||
| verifier-generic-types-2.mir | ||
| verifier-implicit-virtreg-invalid-physreg-liveness.mir | ||
| verifier-phi-fail0.mir | ||
| verifier-phi.mir | ||
| verifier-pseudo-terminators.mir | ||
| verifier-statepoint.mir | ||
| verify-regbankselected.mir | ||
| verify-regops.mir | ||
| verify-selected.mir | ||