forked from OSchip/llvm-project
99 lines
3.2 KiB
TableGen
99 lines
3.2 KiB
TableGen
//===-- MipsMTInstrInfo.td - Mips MT Instruction Infos -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Encodings
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//===----------------------------------------------------------------------===//
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class DMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
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OPCODE_SC_D>;
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class EMT_ENC : COP0_MFMC0_MT<FIELD5_1_DMT_EMT, FIELD5_2_DMT_EMT,
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OPCODE_SC_E>;
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class DVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
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OPCODE_SC_D>;
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class EVPE_ENC : COP0_MFMC0_MT<FIELD5_1_2_DVPE_EVPE, FIELD5_1_2_DVPE_EVPE,
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OPCODE_SC_E>;
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class FORK_ENC : SPECIAL3_MT_FORK;
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class YIELD_ENC : SPECIAL3_MT_YIELD;
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Descriptions
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//===----------------------------------------------------------------------===//
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class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins);
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string AsmString = !strconcat(instr_asm, "\t$rt");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = Itin;
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}
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class FORK_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt);
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string AsmString = "fork\t$rd, $rs, $rt";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_FORK;
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}
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class YIELD_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rs);
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string AsmString = "yield\t$rd, $rs";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_YIELD;
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}
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class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
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class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
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class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;
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class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Definitions
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 1, isNotDuplicable = 1,
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AdditionalPredicates = [NotInMicroMips] in {
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def DMT : DMT_ENC, DMT_DESC, ASE_MT;
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def EMT : EMT_ENC, EMT_DESC, ASE_MT;
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def DVPE : DVPE_ENC, DVPE_DESC, ASE_MT;
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def EVPE : EVPE_ENC, EVPE_DESC, ASE_MT;
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def FORK : FORK_ENC, FORK_DESC, ASE_MT;
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def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
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}
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Definitions
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"dmt", (DMT ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"emt", (EMT ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"dvpe", (DVPE ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
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def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
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}
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