forked from OSchip/llvm-project
200 lines
6.3 KiB
C++
200 lines
6.3 KiB
C++
//===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPULegalizerInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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using namespace LegalizeActions;
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AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
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const GCNTargetMachine &TM) {
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using namespace TargetOpcode;
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auto GetAddrSpacePtr = [&TM](unsigned AS) {
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return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
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};
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auto AMDGPUAS = ST.getAMDGPUAS();
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const LLT S1 = LLT::scalar(1);
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const LLT V2S16 = LLT::vector(2, 16);
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const LLT S32 = LLT::scalar(32);
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const LLT S64 = LLT::scalar(64);
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const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
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const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
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const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
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const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS.FLAT_ADDRESS);
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const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS.PRIVATE_ADDRESS);
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const LLT AddrSpaces[] = {
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GlobalPtr,
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ConstantPtr,
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LocalPtr,
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FlatPtr,
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PrivatePtr
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};
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setAction({G_ADD, S32}, Legal);
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setAction({G_SUB, S32}, Legal);
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setAction({G_MUL, S32}, Legal);
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setAction({G_AND, S32}, Legal);
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setAction({G_OR, S32}, Legal);
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setAction({G_XOR, S32}, Legal);
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setAction({G_BITCAST, V2S16}, Legal);
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setAction({G_BITCAST, 1, S32}, Legal);
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setAction({G_BITCAST, S32}, Legal);
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setAction({G_BITCAST, 1, V2S16}, Legal);
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({S32, S64});
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getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_CONSTANT})
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.legalFor({S1, S32, S64});
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// FIXME: i1 operands to intrinsics should always be legal, but other i1
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// values may not be legal. We need to figure out how to distinguish
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// between these two scenarios.
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setAction({G_CONSTANT, S1}, Legal);
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setAction({G_FADD, S32}, Legal);
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setAction({G_FCMP, S1}, Legal);
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setAction({G_FCMP, 1, S32}, Legal);
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setAction({G_FCMP, 1, S64}, Legal);
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setAction({G_FMUL, S32}, Legal);
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setAction({G_ZEXT, S64}, Legal);
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setAction({G_ZEXT, 1, S32}, Legal);
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setAction({G_FPTOSI, S32}, Legal);
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setAction({G_FPTOSI, 1, S32}, Legal);
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setAction({G_FPTOUI, S32}, Legal);
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setAction({G_FPTOUI, 1, S32}, Legal);
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for (LLT PtrTy : AddrSpaces) {
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LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
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setAction({G_GEP, PtrTy}, Legal);
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setAction({G_GEP, 1, IdxTy}, Legal);
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}
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setAction({G_ICMP, S1}, Legal);
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setAction({G_ICMP, 1, S32}, Legal);
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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const LLT &Ty0 = Query.Types[0];
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// TODO: Decompose private loads into 4-byte components.
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// TODO: Illegal flat loads on SI
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switch (Ty0.getSizeInBits()) {
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case 32:
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case 64:
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case 128:
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return true;
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case 96:
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// XXX hasLoadX3
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return (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS);
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case 256:
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case 512:
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// TODO: constant loads
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default:
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return false;
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}
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});
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setAction({G_SELECT, S32}, Legal);
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setAction({G_SELECT, 1, S1}, Legal);
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setAction({G_SHL, S32}, Legal);
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// FIXME: When RegBankSelect inserts copies, it will only create new
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// registers with scalar types. This means we can end up with
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// G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
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// operands. In assert builds, the instruction selector will assert
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// if it sees a generic instruction which isn't legal, so we need to
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// tell it that scalar types are legal for pointer operands
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setAction({G_GEP, S64}, Legal);
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for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
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getActionDefinitionsBuilder(Op)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &VecTy = Query.Types[1];
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const LLT &IdxTy = Query.Types[2];
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return VecTy.getSizeInBits() % 32 == 0 &&
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VecTy.getSizeInBits() <= 512 &&
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IdxTy.getSizeInBits() == 32;
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});
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}
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// FIXME: Doesn't handle extract of illegal sizes.
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getActionDefinitionsBuilder(G_EXTRACT)
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.unsupportedIf([=](const LegalityQuery &Query) {
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return Query.Types[0].getSizeInBits() >= Query.Types[1].getSizeInBits();
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})
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &Ty0 = Query.Types[0];
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const LLT &Ty1 = Query.Types[1];
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return (Ty0.getSizeInBits() % 32 == 0) &&
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(Ty1.getSizeInBits() % 32 == 0);
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});
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// Merge/Unmerge
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for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
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unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
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unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
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getActionDefinitionsBuilder(Op)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &BigTy = Query.Types[BigTyIdx];
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const LLT &LitTy = Query.Types[LitTyIdx];
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return BigTy.getSizeInBits() % 32 == 0 &&
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LitTy.getSizeInBits() % 32 == 0 &&
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BigTy.getSizeInBits() <= 512;
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})
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// Any vectors left are the wrong size. Scalarize them.
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.fewerElementsIf([](const LegalityQuery &Query) { return true; },
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[](const LegalityQuery &Query) {
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return std::make_pair(
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0, Query.Types[0].getElementType());
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})
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.fewerElementsIf([](const LegalityQuery &Query) { return true; },
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[](const LegalityQuery &Query) {
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return std::make_pair(
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1, Query.Types[1].getElementType());
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});
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}
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computeTables();
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verify(*ST.getInstrInfo());
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}
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