forked from OSchip/llvm-project
102 lines
3.2 KiB
C++
102 lines
3.2 KiB
C++
//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for
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/// AMDGPU.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#include "AMDGPU.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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}
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namespace llvm {
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class AMDGPUInstrInfo;
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class AMDGPURegisterBankInfo;
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class AMDGPUSubtarget;
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class SIInstrInfo;
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class SIRegisterInfo;
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class SISubtarget;
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class AMDGPUInstructionSelector : public InstructionSelector {
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public:
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AMDGPUInstructionSelector(const SISubtarget &STI,
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const AMDGPURegisterBankInfo &RBI,
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const AMDGPUTargetMachine &TM);
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bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
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static const char *getName();
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private:
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struct GEPInfo {
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const MachineInstr &GEP;
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SmallVector<unsigned, 2> SgprParts;
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SmallVector<unsigned, 2> VgprParts;
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int64_t Imm;
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GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
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};
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/// tblgen-erated 'select' implementation.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
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bool selectCOPY(MachineInstr &I) const;
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bool selectG_CONSTANT(MachineInstr &I) const;
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bool selectG_ADD(MachineInstr &I) const;
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bool selectG_GEP(MachineInstr &I) const;
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bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
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void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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SmallVectorImpl<GEPInfo> &AddrInfo) const;
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bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
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bool selectG_LOAD(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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InstructionSelector::ComplexRendererFns
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selectVSRC0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods(MachineOperand &Root) const;
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const SIInstrInfo &TII;
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const SIRegisterInfo &TRI;
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const AMDGPURegisterBankInfo &RBI;
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const AMDGPUTargetMachine &TM;
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const SISubtarget &STI;
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bool EnableLateStructurizeCFG;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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protected:
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AMDGPUAS AMDGPUASI;
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};
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} // End llvm namespace.
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#endif
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