Amara Emerson 7d5b103483 [AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b. ... In order to not unnecessarily promote the source vector to greater than our native vector size of 128b, I've added some cascading rules to widen based on the number of elements.		2020-09-17 11:50:33 -07:00
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AArch64	[AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b.	2020-09-17 11:50:33 -07:00
AMDGPU	[amdgpu] Lower SGPR-to-VGPR copy in the final phase of ISel.	2020-09-17 11:04:17 -04:00
ARC	[ARC] Update brcc test.	2020-08-28 17:07:25 -07:00
ARM	[ARM][MachineOutliner] Add missing testcase for calls.	2020-09-17 15:20:21 +02:00
AVR	…
BPF	…
Generic	[Intrinsics] define semantics for experimental fmax/fmin vector reductions	2020-09-12 09:10:28 -04:00
Hexagon	[Hexagon] Replace incorrect pattern for vpackl HWI32 -> HVi8	2020-09-15 20:34:50 -05:00
Inputs	…
Lanai	…
MIR	[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)	2020-09-03 16:13:09 -04:00
MSP430	…
Mips	Revert "RegAllocFast: Record internal state based on register units"	2020-09-15 13:25:41 +02:00
NVPTX	[NVPTX] Fix typo in lit test	2020-08-17 16:02:11 -04:00
PowerPC	[PowerPC][AIX] Don't hardcode python invoke command line	2020-09-17 17:47:41 +00:00
RISCV	[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move	2020-08-27 10:32:22 +01:00
SPARC	Revert "RegAllocFast: Record internal state based on register units"	2020-09-15 13:25:41 +02:00
SystemZ	[SelectionDAGBuilder] Pass fast math flags to getNode calls rather than trying to set them after the fact.:	2020-09-08 15:27:21 -07:00
Thumb	…
Thumb2	[ARM] Expand distributing increments to also handle existing pre/post inc instructions.	2020-09-17 16:58:35 +01:00
VE	[VE] Support f128	2020-08-17 17:26:52 +09:00
WebAssembly	[WebAssembly] Fix fixEndsAtEndOfFunction for try-catch	2020-09-08 09:27:40 -07:00
WinCFGuard	…
WinEH	…
X86	[X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber	2020-09-17 11:26:50 -07:00
XCore	…