forked from OSchip/llvm-project
472 lines
18 KiB
C++
472 lines
18 KiB
C++
//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the JIT interfaces for the 32-bit PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "jit"
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#include "PPCJITInfo.h"
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#include "PPCRelocations.h"
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#include "PPCTargetMachine.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Memory.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static TargetJITInfo::JITCompilerFn JITCompilerFunction;
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#define BUILD_ADDIS(RD,RS,IMM16) \
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((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
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#define BUILD_ORI(RD,RS,UIMM16) \
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((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
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#define BUILD_ORIS(RD,RS,UIMM16) \
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((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
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#define BUILD_RLDICR(RD,RS,SH,ME) \
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((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
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(((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1))
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#define BUILD_MTSPR(RS,SPR) \
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((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
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#define BUILD_BCCTRx(BO,BI,LINK) \
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((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
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#define BUILD_B(TARGET, LINK) \
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((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
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// Pseudo-ops
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#define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
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#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
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#define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9)
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#define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK)
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static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
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intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
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unsigned *AtI = (unsigned*)(intptr_t)At;
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if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
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AtI[0] = BUILD_B(Offset, isCall); // b/bl target
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} else if (!is64Bit) {
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AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address)
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AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
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AtI[2] = BUILD_MTCTR(12); // mtctr r12
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AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl
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} else {
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AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address)
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AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address)
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AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32
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AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
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AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
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AtI[5] = BUILD_MTCTR(12); // mtctr r12
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AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl
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}
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}
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extern "C" void PPC32CompilationCallback();
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extern "C" void PPC64CompilationCallback();
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#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
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!(defined(__ppc64__) || defined(__FreeBSD__))
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// CompilationCallback stub - We can't use a C function with inline assembly in
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// it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
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// write our own wrapper, which does things our way, so we have complete control
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// over register saving and restoring.
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asm(
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".text\n"
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".align 2\n"
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".globl _PPC32CompilationCallback\n"
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"_PPC32CompilationCallback:\n"
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// Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
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// FIXME: need to save v[0-19] for altivec?
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// FIXME: could shrink frame
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// Set up a proper stack frame
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// FIXME Layout
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// PowerPC32 ABI linkage - 24 bytes
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// parameters - 32 bytes
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// 13 double registers - 104 bytes
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// 8 int registers - 32 bytes
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"mflr r0\n"
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"stw r0, 8(r1)\n"
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"stwu r1, -208(r1)\n"
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// Save all int arg registers
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"stw r10, 204(r1)\n" "stw r9, 200(r1)\n"
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"stw r8, 196(r1)\n" "stw r7, 192(r1)\n"
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"stw r6, 188(r1)\n" "stw r5, 184(r1)\n"
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"stw r4, 180(r1)\n" "stw r3, 176(r1)\n"
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// Save all call-clobbered FP regs.
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"stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n"
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"stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n"
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"stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n"
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"stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n"
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"stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n"
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"stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n"
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"stfd f1, 72(r1)\n"
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// Arguments to Compilation Callback:
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// r3 - our lr (address of the call instruction in stub plus 4)
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// r4 - stub's lr (address of instruction that called the stub plus 4)
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// r5 - is64Bit - always 0.
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"mr r3, r0\n"
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"lwz r2, 208(r1)\n" // stub's frame
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"lwz r4, 8(r2)\n" // stub's lr
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"li r5, 0\n" // 0 == 32 bit
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"bl _LLVMPPCCompilationCallback\n"
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"mtctr r3\n"
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// Restore all int arg registers
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"lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n"
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"lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n"
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"lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n"
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"lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n"
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// Restore all FP arg registers
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"lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n"
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"lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n"
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"lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n"
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"lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n"
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"lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n"
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"lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n"
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"lfd f1, 72(r1)\n"
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// Pop 3 frames off the stack and branch to target
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"lwz r1, 208(r1)\n"
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"lwz r2, 8(r1)\n"
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"mtlr r2\n"
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"bctr\n"
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);
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#elif defined(__PPC__) && !defined(__ppc64__)
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// Linux & FreeBSD / PPC 32 support
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// CompilationCallback stub - We can't use a C function with inline assembly in
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// it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
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// write our own wrapper, which does things our way, so we have complete control
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// over register saving and restoring.
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asm(
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".text\n"
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".align 2\n"
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".globl PPC32CompilationCallback\n"
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"PPC32CompilationCallback:\n"
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// Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the
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// FIXME: need to save v[0-19] for altivec?
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// FIXME: could shrink frame
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// Set up a proper stack frame
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// FIXME Layout
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// 8 double registers - 64 bytes
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// 8 int registers - 32 bytes
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"mflr 0\n"
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"stw 0, 4(1)\n"
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"stwu 1, -104(1)\n"
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// Save all int arg registers
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"stw 10, 100(1)\n" "stw 9, 96(1)\n"
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"stw 8, 92(1)\n" "stw 7, 88(1)\n"
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"stw 6, 84(1)\n" "stw 5, 80(1)\n"
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"stw 4, 76(1)\n" "stw 3, 72(1)\n"
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// Save all call-clobbered FP regs.
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"stfd 8, 64(1)\n"
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"stfd 7, 56(1)\n" "stfd 6, 48(1)\n"
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"stfd 5, 40(1)\n" "stfd 4, 32(1)\n"
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"stfd 3, 24(1)\n" "stfd 2, 16(1)\n"
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"stfd 1, 8(1)\n"
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// Arguments to Compilation Callback:
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// r3 - our lr (address of the call instruction in stub plus 4)
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// r4 - stub's lr (address of instruction that called the stub plus 4)
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// r5 - is64Bit - always 0.
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"mr 3, 0\n"
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"lwz 5, 104(1)\n" // stub's frame
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"lwz 4, 4(5)\n" // stub's lr
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"li 5, 0\n" // 0 == 32 bit
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"bl LLVMPPCCompilationCallback\n"
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"mtctr 3\n"
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// Restore all int arg registers
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"lwz 10, 100(1)\n" "lwz 9, 96(1)\n"
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"lwz 8, 92(1)\n" "lwz 7, 88(1)\n"
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"lwz 6, 84(1)\n" "lwz 5, 80(1)\n"
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"lwz 4, 76(1)\n" "lwz 3, 72(1)\n"
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// Restore all FP arg registers
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"lfd 8, 64(1)\n"
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"lfd 7, 56(1)\n" "lfd 6, 48(1)\n"
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"lfd 5, 40(1)\n" "lfd 4, 32(1)\n"
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"lfd 3, 24(1)\n" "lfd 2, 16(1)\n"
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"lfd 1, 8(1)\n"
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// Pop 3 frames off the stack and branch to target
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"lwz 1, 104(1)\n"
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"lwz 0, 4(1)\n"
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"mtlr 0\n"
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"bctr\n"
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);
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#else
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void PPC32CompilationCallback() {
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llvm_unreachable("This is not a power pc, you can't execute this!");
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}
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#endif
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#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
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defined(__ppc64__)
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#ifdef __ELF__
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asm(
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".text\n"
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".align 2\n"
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".globl PPC64CompilationCallback\n"
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".section \".opd\",\"aw\",@progbits\n"
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".align 3\n"
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"PPC64CompilationCallback:\n"
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".quad .L.PPC64CompilationCallback,.TOC.@tocbase,0\n"
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".size PPC64CompilationCallback,24\n"
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".previous\n"
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".align 4\n"
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".type PPC64CompilationCallback,@function\n"
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".L.PPC64CompilationCallback:\n"
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#else
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asm(
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".text\n"
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".align 2\n"
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".globl _PPC64CompilationCallback\n"
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"_PPC64CompilationCallback:\n"
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#endif
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// Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
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// FIXME: need to save v[0-19] for altivec?
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// Set up a proper stack frame
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// Layout
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// PowerPC64 ABI linkage - 48 bytes
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// parameters - 64 bytes
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// 13 double registers - 104 bytes
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// 8 int registers - 64 bytes
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"mflr 0\n"
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"std 0, 16(1)\n"
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"stdu 1, -280(1)\n"
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// Save all int arg registers
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"std 10, 272(1)\n" "std 9, 264(1)\n"
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"std 8, 256(1)\n" "std 7, 248(1)\n"
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"std 6, 240(1)\n" "std 5, 232(1)\n"
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"std 4, 224(1)\n" "std 3, 216(1)\n"
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// Save all call-clobbered FP regs.
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"stfd 13, 208(1)\n" "stfd 12, 200(1)\n"
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"stfd 11, 192(1)\n" "stfd 10, 184(1)\n"
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"stfd 9, 176(1)\n" "stfd 8, 168(1)\n"
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"stfd 7, 160(1)\n" "stfd 6, 152(1)\n"
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"stfd 5, 144(1)\n" "stfd 4, 136(1)\n"
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"stfd 3, 128(1)\n" "stfd 2, 120(1)\n"
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"stfd 1, 112(1)\n"
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// Arguments to Compilation Callback:
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// r3 - our lr (address of the call instruction in stub plus 4)
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// r4 - stub's lr (address of instruction that called the stub plus 4)
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// r5 - is64Bit - always 1.
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"mr 3, 0\n" // return address (still in r0)
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"ld 5, 280(1)\n" // stub's frame
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"ld 4, 16(5)\n" // stub's lr
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"li 5, 1\n" // 1 == 64 bit
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#ifdef __ELF__
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"bl LLVMPPCCompilationCallback\n"
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"nop\n"
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#else
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"bl _LLVMPPCCompilationCallback\n"
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#endif
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"mtctr 3\n"
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// Restore all int arg registers
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"ld 10, 272(1)\n" "ld 9, 264(1)\n"
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"ld 8, 256(1)\n" "ld 7, 248(1)\n"
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"ld 6, 240(1)\n" "ld 5, 232(1)\n"
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"ld 4, 224(1)\n" "ld 3, 216(1)\n"
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// Restore all FP arg registers
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"lfd 13, 208(1)\n" "lfd 12, 200(1)\n"
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"lfd 11, 192(1)\n" "lfd 10, 184(1)\n"
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"lfd 9, 176(1)\n" "lfd 8, 168(1)\n"
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"lfd 7, 160(1)\n" "lfd 6, 152(1)\n"
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"lfd 5, 144(1)\n" "lfd 4, 136(1)\n"
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"lfd 3, 128(1)\n" "lfd 2, 120(1)\n"
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"lfd 1, 112(1)\n"
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// Pop 3 frames off the stack and branch to target
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"ld 1, 280(1)\n"
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"ld 0, 16(1)\n"
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"mtlr 0\n"
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// XXX: any special TOC handling in the ELF case for JIT?
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"bctr\n"
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);
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#else
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void PPC64CompilationCallback() {
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llvm_unreachable("This is not a power pc, you can't execute this!");
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}
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#endif
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extern "C" {
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LLVM_LIBRARY_VISIBILITY void *
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LLVMPPCCompilationCallback(unsigned *StubCallAddrPlus4,
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unsigned *OrigCallAddrPlus4,
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bool is64Bit) {
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// Adjust the pointer to the address of the call instruction in the stub
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// emitted by emitFunctionStub, rather than the instruction after it.
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unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
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unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
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void *Target = JITCompilerFunction(StubCallAddr);
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// Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
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// it to branch directly to the destination. If so, rewrite it so it does not
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// need to go through the stub anymore.
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unsigned OrigCallInst = *OrigCallAddr;
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if ((OrigCallInst >> 26) == 18) { // Direct call.
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intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
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if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
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// Clear the original target out.
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OrigCallInst &= (63 << 26) | 3;
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// Fill in the new target.
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OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
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// Replace the call.
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*OrigCallAddr = OrigCallInst;
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}
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}
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// Assert that we are coming from a stub that was created with our
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// emitFunctionStub.
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if ((*StubCallAddr >> 26) == 18)
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StubCallAddr -= 3;
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else {
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assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
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StubCallAddr -= is64Bit ? 9 : 6;
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}
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// Rewrite the stub with an unconditional branch to the target, for any users
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// who took the address of the stub.
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EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
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sys::Memory::InvalidateInstructionCache(StubCallAddr, 7*4);
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// Put the address of the target function to call and the address to return to
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// after calling the target function in a place that is easy to get on the
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// stack after we restore all regs.
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return Target;
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}
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}
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TargetJITInfo::LazyResolverFn
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PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
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JITCompilerFunction = Fn;
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return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
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}
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TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() {
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// The stub contains up to 10 4-byte instructions, aligned at 4 bytes: 3
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// instructions to save the caller's address if this is a lazy-compilation
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// stub, plus a 1-, 4-, or 7-instruction sequence to load an arbitrary address
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// into a register and jump through it.
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StubLayout Result = {10*4, 4};
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return Result;
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}
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#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
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defined(__APPLE__)
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extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
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#endif
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void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn,
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JITCodeEmitter &JCE) {
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// If this is just a call to an external function, emit a branch instead of a
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// call. The code is the same except for one bit of the last instruction.
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if (Fn != (void*)(intptr_t)PPC32CompilationCallback &&
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Fn != (void*)(intptr_t)PPC64CompilationCallback) {
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void *Addr = (void*)JCE.getCurrentPCValue();
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JCE.emitWordBE(0);
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JCE.emitWordBE(0);
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JCE.emitWordBE(0);
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JCE.emitWordBE(0);
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JCE.emitWordBE(0);
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JCE.emitWordBE(0);
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JCE.emitWordBE(0);
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EmitBranchToAt((intptr_t)Addr, (intptr_t)Fn, false, is64Bit);
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sys::Memory::InvalidateInstructionCache(Addr, 7*4);
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return Addr;
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}
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void *Addr = (void*)JCE.getCurrentPCValue();
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if (is64Bit) {
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JCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1)
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JCE.emitWordBE(0x7d6802a6); // mflr r11
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JCE.emitWordBE(0xf9610060); // std r11, 96(r1)
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|
} else if (TM.getSubtargetImpl()->isDarwinABI()){
|
|
JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
|
|
JCE.emitWordBE(0x7d6802a6); // mflr r11
|
|
JCE.emitWordBE(0x91610028); // stw r11, 40(r1)
|
|
} else {
|
|
JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
|
|
JCE.emitWordBE(0x7d6802a6); // mflr r11
|
|
JCE.emitWordBE(0x91610024); // stw r11, 36(r1)
|
|
}
|
|
intptr_t BranchAddr = (intptr_t)JCE.getCurrentPCValue();
|
|
JCE.emitWordBE(0);
|
|
JCE.emitWordBE(0);
|
|
JCE.emitWordBE(0);
|
|
JCE.emitWordBE(0);
|
|
JCE.emitWordBE(0);
|
|
JCE.emitWordBE(0);
|
|
JCE.emitWordBE(0);
|
|
EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit);
|
|
sys::Memory::InvalidateInstructionCache(Addr, 10*4);
|
|
return Addr;
|
|
}
|
|
|
|
|
|
void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
|
|
unsigned NumRelocs, unsigned char* GOTBase) {
|
|
for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
|
|
unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
|
|
intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
|
|
switch ((PPC::RelocationType)MR->getRelocationType()) {
|
|
default: llvm_unreachable("Unknown relocation type!");
|
|
case PPC::reloc_pcrel_bx:
|
|
// PC-relative relocation for b and bl instructions.
|
|
ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
|
|
assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
|
|
"Relocation out of range!");
|
|
*RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2;
|
|
break;
|
|
case PPC::reloc_pcrel_bcx:
|
|
// PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
|
|
// bcx instructions.
|
|
ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
|
|
assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
|
|
"Relocation out of range!");
|
|
*RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2;
|
|
break;
|
|
case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr
|
|
case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr
|
|
ResultPtr += MR->getConstantVal();
|
|
|
|
// If this is a high-part access, get the high-part.
|
|
if (MR->getRelocationType() == PPC::reloc_absolute_high) {
|
|
// If the low part will have a carry (really a borrow) from the low
|
|
// 16-bits into the high 16, add a bit to borrow from.
|
|
if (((int)ResultPtr << 16) < 0)
|
|
ResultPtr += 1 << 16;
|
|
ResultPtr >>= 16;
|
|
}
|
|
|
|
// Do the addition then mask, so the addition does not overflow the 16-bit
|
|
// immediate section of the instruction.
|
|
unsigned LowBits = (*RelocPos + ResultPtr) & 65535;
|
|
unsigned HighBits = *RelocPos & ~65535;
|
|
*RelocPos = LowBits | HighBits; // Slam into low 16-bits
|
|
break;
|
|
}
|
|
case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr
|
|
ResultPtr += MR->getConstantVal();
|
|
// Do the addition then mask, so the addition does not overflow the 16-bit
|
|
// immediate section of the instruction.
|
|
unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC;
|
|
unsigned HighBits = *RelocPos & 0xFFFF0003;
|
|
*RelocPos = LowBits | HighBits; // Slam into low 14-bits.
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
|
|
EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
|
|
sys::Memory::InvalidateInstructionCache(Old, 7*4);
|
|
}
|