forked from OSchip/llvm-project
686 lines
14 KiB
TableGen
686 lines
14 KiB
TableGen
//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MIPS instructions format
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//
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// CPU INSTRUCTION FORMATS
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//
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// opcode - operation code.
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// rs - src reg.
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// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
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// rd - dst reg, only used on 3 regs instr.
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// shamt - only used on shift instructions, contains the shift amount.
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// funct - combined with opcode field give us an operation code.
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<4> val> {
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bits<4> Value = val;
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}
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def Pseudo : Format<0>;
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def FrmR : Format<1>;
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def FrmI : Format<2>;
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def FrmJ : Format<3>;
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def FrmFR : Format<4>;
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def FrmFI : Format<5>;
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def FrmOther : Format<6>; // Instruction w/ a custom format
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class MMRel;
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def Std2MicroMips : InstrMapping {
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let FilterClass = "MMRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["Arch"];
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// The key column is the unpredicated instructions.
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let KeyCol = ["se"];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["se"], ["micromips"]];
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}
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class StdArch {
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string Arch = "se";
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}
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// Generic Mips Format
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class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>: Instruction
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{
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field bits<32> Inst;
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Format Form = f;
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let Namespace = "Mips";
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let Size = 4;
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bits<6> Opcode = 0;
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// Top 6 bits are the 'opcode' field
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let Inst{31-26} = Opcode;
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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//
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// Attributes specific to Mips instructions...
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//
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bits<4> FormBits = Form.Value;
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{3-0} = FormBits;
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let DecoderNamespace = "Mips";
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field bits<32> SoftFail = 0;
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}
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// Mips32/64 Instruction Format
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class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f, string opstr = ""> :
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MipsInst<outs, ins, asmstr, pattern, itin, f> {
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let Predicates = [HasStdEnc];
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string BaseOpcode = opstr;
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string Arch;
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}
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// Mips Pseudo Instructions Format
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class MipsPseudo<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo> :
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MipsInst<outs, ins, "", pattern, itin, Pseudo> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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// Mips32/64 Pseudo Instruction Format
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class PseudoSE<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo>:
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MipsPseudo<outs, ins, pattern, itin> {
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let Predicates = [HasStdEnc];
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}
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
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MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
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let isPseudo = 1;
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let Pattern = [];
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}
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//===----------------------------------------------------------------------===//
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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//===----------------------------------------------------------------------===//
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class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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InstSE<outs, ins, asmstr, pattern, itin, FrmR>
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{
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<5> shamt;
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bits<6> funct;
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let Opcode = op;
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let funct = _funct;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = shamt;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
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//===----------------------------------------------------------------------===//
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class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
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{
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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let Opcode = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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InstSE<outs, ins, asmstr, pattern, itin, FrmI>
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{
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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let Opcode = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// Format J instruction class in Mips : <|opcode|address|>
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//===----------------------------------------------------------------------===//
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class FJ<bits<6> op>
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{
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bits<26> target;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-0} = target;
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}
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//===----------------------------------------------------------------------===//
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// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
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//===----------------------------------------------------------------------===//
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class MFC3OP_FM<bits<6> op, bits<5> mfmt>
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{
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bits<5> rt;
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bits<5> rd;
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bits<3> sel;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = mfmt;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-3} = 0;
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let Inst{2-0} = sel;
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}
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class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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class ADDI_FM<bits<6> op> : StdArch {
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class SRA_FM<bits<6> funct, bit rotate> : StdArch {
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bits<5> rd;
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bits<5> rt;
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bits<5> shamt;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-22} = 0;
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let Inst{21} = rotate;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = shamt;
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let Inst{5-0} = funct;
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}
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class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
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bits<5> rd;
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bits<5> rt;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-7} = 0;
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let Inst{6} = rotate;
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let Inst{5-0} = funct;
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}
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class BEQ_FM<bits<6> op> {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class BGEZ_FM<bits<6> op, bits<5> funct> {
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = funct;
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let Inst{15-0} = offset;
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}
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class B_FM {
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 4;
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let Inst{25-21} = 0;
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let Inst{20-16} = 0;
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let Inst{15-0} = offset;
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}
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class SLTI_FM<bits<6> op> : StdArch {
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class MFLO_FM<bits<6> funct> {
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bits<5> rd;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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}
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class MTLO_FM<bits<6> funct> {
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-6} = 0;
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let Inst{5-0} = funct;
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}
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class SEB_FM<bits<5> funct, bits<6> funct2> {
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bits<5> rd;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0x1f;
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let Inst{25-21} = 0;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = funct;
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let Inst{5-0} = funct2;
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}
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class CLO_FM<bits<6> funct> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0x1c;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = funct;
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let rt = rd;
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}
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class LUI_FM {
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bits<5> rt;
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bits<16> imm16;
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bits<32> Inst;
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let Inst{31-26} = 0xf;
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let Inst{25-21} = 0;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class JALR_FM {
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bits<5> rd;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = 9;
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}
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class BAL_FM {
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 1;
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let Inst{25-21} = 0;
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let Inst{20-16} = 0x11;
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let Inst{15-0} = offset;
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}
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class BGEZAL_FM<bits<5> funct> {
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bits<5> rs;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 1;
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let Inst{25-21} = rs;
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let Inst{20-16} = funct;
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let Inst{15-0} = offset;
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}
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class SYNC_FM {
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bits<5> stype;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{10-6} = stype;
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let Inst{5-0} = 0xf;
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}
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class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-6} = 0;
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let Inst{5-0} = funct;
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}
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class EXT_FM<bits<6> funct> {
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bits<5> rt;
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bits<5> rs;
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bits<5> pos;
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bits<5> size;
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bits<32> Inst;
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let Inst{31-26} = 0x1f;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = size;
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let Inst{10-6} = pos;
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let Inst{5-0} = funct;
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}
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class RDHWR_FM {
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bits<5> rt;
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bits<5> rd;
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bits<32> Inst;
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let Inst{31-26} = 0x1f;
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let Inst{25-21} = 0;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = 0x3b;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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//
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// opcode - operation code.
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// fs - src reg.
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// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
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// fd - dst reg, only used on 3 regs instr.
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// fmt - double or single precision.
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// funct - combined with opcode field give us an operation code.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
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//===----------------------------------------------------------------------===//
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class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
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{
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bits<5> ft;
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bits<5> base;
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bits<16> imm16;
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let Opcode = op;
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let Inst{25-21} = base;
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let Inst{20-16} = ft;
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let Inst{15-0} = imm16;
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}
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class ADDS_FM<bits<6> funct, bits<5> fmt> {
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bits<5> fd;
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bits<5> fs;
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bits<5> ft;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = fmt;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class ABSS_FM<bits<6> funct, bits<5> fmt> {
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bits<5> fd;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = fmt;
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let Inst{20-16} = 0;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class MFC1_FM<bits<5> funct> {
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bits<5> rt;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = funct;
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let Inst{20-16} = rt;
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let Inst{15-11} = fs;
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let Inst{10-0} = 0;
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}
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class LW_FM<bits<6> op> : StdArch {
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bits<5> rt;
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bits<21> addr;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = addr{20-16};
|
|
let Inst{20-16} = rt;
|
|
let Inst{15-0} = addr{15-0};
|
|
}
|
|
|
|
class MADDS_FM<bits<3> funct, bits<3> fmt> {
|
|
bits<5> fd;
|
|
bits<5> fr;
|
|
bits<5> fs;
|
|
bits<5> ft;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x13;
|
|
let Inst{25-21} = fr;
|
|
let Inst{20-16} = ft;
|
|
let Inst{15-11} = fs;
|
|
let Inst{10-6} = fd;
|
|
let Inst{5-3} = funct;
|
|
let Inst{2-0} = fmt;
|
|
}
|
|
|
|
class LWXC1_FM<bits<6> funct> {
|
|
bits<5> fd;
|
|
bits<5> base;
|
|
bits<5> index;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x13;
|
|
let Inst{25-21} = base;
|
|
let Inst{20-16} = index;
|
|
let Inst{15-11} = 0;
|
|
let Inst{10-6} = fd;
|
|
let Inst{5-0} = funct;
|
|
}
|
|
|
|
class SWXC1_FM<bits<6> funct> {
|
|
bits<5> fs;
|
|
bits<5> base;
|
|
bits<5> index;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x13;
|
|
let Inst{25-21} = base;
|
|
let Inst{20-16} = index;
|
|
let Inst{15-11} = fs;
|
|
let Inst{10-6} = 0;
|
|
let Inst{5-0} = funct;
|
|
}
|
|
|
|
class BC1F_FM<bit nd, bit tf> {
|
|
bits<16> offset;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x11;
|
|
let Inst{25-21} = 0x8;
|
|
let Inst{20-18} = 0; // cc
|
|
let Inst{17} = nd;
|
|
let Inst{16} = tf;
|
|
let Inst{15-0} = offset;
|
|
}
|
|
|
|
class CEQS_FM<bits<5> fmt> {
|
|
bits<5> fs;
|
|
bits<5> ft;
|
|
bits<4> cond;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x11;
|
|
let Inst{25-21} = fmt;
|
|
let Inst{20-16} = ft;
|
|
let Inst{15-11} = fs;
|
|
let Inst{10-8} = 0; // cc
|
|
let Inst{7-4} = 0x3;
|
|
let Inst{3-0} = cond;
|
|
}
|
|
|
|
class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
|
|
bits<5> fd;
|
|
bits<5> fs;
|
|
bits<5> rt;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x11;
|
|
let Inst{25-21} = fmt;
|
|
let Inst{20-16} = rt;
|
|
let Inst{15-11} = fs;
|
|
let Inst{10-6} = fd;
|
|
let Inst{5-0} = funct;
|
|
}
|
|
|
|
class CMov_F_I_FM<bit tf> {
|
|
bits<5> rd;
|
|
bits<5> rs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0;
|
|
let Inst{25-21} = rs;
|
|
let Inst{20-18} = 0; // cc
|
|
let Inst{17} = 0;
|
|
let Inst{16} = tf;
|
|
let Inst{15-11} = rd;
|
|
let Inst{10-6} = 0;
|
|
let Inst{5-0} = 1;
|
|
}
|
|
|
|
class CMov_F_F_FM<bits<5> fmt, bit tf> {
|
|
bits<5> fd;
|
|
bits<5> fs;
|
|
|
|
bits<32> Inst;
|
|
|
|
let Inst{31-26} = 0x11;
|
|
let Inst{25-21} = fmt;
|
|
let Inst{20-18} = 0; // cc
|
|
let Inst{17} = 0;
|
|
let Inst{16} = tf;
|
|
let Inst{15-11} = fs;
|
|
let Inst{10-6} = fd;
|
|
let Inst{5-0} = 0x11;
|
|
}
|