forked from OSchip/llvm-project
401 lines
13 KiB
LLVM
401 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
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; SSE3-LABEL: haddpd1:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddpd %xmm1, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddpd1:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
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%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
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; SSE3-LABEL: haddpd2:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddpd %xmm1, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddpd2:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
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%b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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define <2 x double> @haddpd3(<2 x double> %x) {
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; SSE3-LABEL: haddpd3:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddpd %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddpd3:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
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; SSE3-LABEL: haddps1:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm1, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps1:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
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; SSE3-LABEL: haddps2:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm1, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps2:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
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%b = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @haddps3(<4 x float> %x) {
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; SSE3-LABEL: haddps3:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps3:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @haddps4(<4 x float> %x) {
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; SSE3-LABEL: haddps4:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps4:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @haddps5(<4 x float> %x) {
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; SSE3-LABEL: haddps5:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps5:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @haddps6(<4 x float> %x) {
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; SSE3-LABEL: haddps6:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps6:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @haddps7(<4 x float> %x) {
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; SSE3-LABEL: haddps7:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: haddps7:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
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; SSE3-LABEL: hsubpd1:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubpd %xmm1, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: hsubpd1:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
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%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
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%r = fsub <2 x double> %a, %b
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ret <2 x double> %r
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}
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define <2 x double> @hsubpd2(<2 x double> %x) {
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; SSE3-LABEL: hsubpd2:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubpd %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: hsubpd2:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%r = fsub <2 x double> %a, %b
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ret <2 x double> %r
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}
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define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
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; SSE3-LABEL: hsubps1:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubps %xmm1, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: hsubps1:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @hsubps2(<4 x float> %x) {
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; SSE3-LABEL: hsubps2:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: hsubps2:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @hsubps3(<4 x float> %x) {
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; SSE3-LABEL: hsubps3:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: hsubps3:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <4 x float> @hsubps4(<4 x float> %x) {
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; SSE3-LABEL: hsubps4:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubps %xmm0, %xmm0
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: hsubps4:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
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; SSE3-LABEL: vhaddps1:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm2, %xmm0
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; SSE3-NEXT: haddps %xmm3, %xmm1
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: vhaddps1:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
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; SSE3-LABEL: vhaddps2:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm2, %xmm0
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; SSE3-NEXT: haddps %xmm3, %xmm1
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: vhaddps2:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
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%b = shufflevector <8 x float> %y, <8 x float> %x, <8 x i32> <i32 8, i32 11, i32 0, i32 3, i32 12, i32 15, i32 4, i32 7>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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define <8 x float> @vhaddps3(<8 x float> %x) {
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; SSE3-LABEL: vhaddps3:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: haddps %xmm1, %xmm1
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: vhaddps3:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %ymm0, %ymm0, %ymm0
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; AVX-NEXT: retq
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%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = fadd <8 x float> %a, %b
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ret <8 x float> %r
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}
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define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
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; SSE3-LABEL: vhsubps1:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubps %xmm2, %xmm0
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; SSE3-NEXT: hsubps %xmm3, %xmm1
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: vhsubps1:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
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%r = fsub <8 x float> %a, %b
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ret <8 x float> %r
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}
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define <8 x float> @vhsubps3(<8 x float> %x) {
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; SSE3-LABEL: vhsubps3:
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; SSE3: # BB#0:
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; SSE3-NEXT: hsubps %xmm0, %xmm0
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; SSE3-NEXT: hsubps %xmm1, %xmm1
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: vhsubps3:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %ymm0, %ymm0, %ymm0
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; AVX-NEXT: retq
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%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
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%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
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%r = fsub <8 x float> %a, %b
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ret <8 x float> %r
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}
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define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
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; SSE3-LABEL: vhaddpd1:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddpd %xmm2, %xmm0
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; SSE3-NEXT: haddpd %xmm3, %xmm1
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: vhaddpd1:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
|
|
%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
%r = fadd <4 x double> %a, %b
|
|
ret <4 x double> %r
|
|
}
|
|
|
|
define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
|
|
; SSE3-LABEL: vhsubpd1:
|
|
; SSE3: # BB#0:
|
|
; SSE3-NEXT: hsubpd %xmm2, %xmm0
|
|
; SSE3-NEXT: hsubpd %xmm3, %xmm1
|
|
; SSE3-NEXT: retq
|
|
;
|
|
; AVX-LABEL: vhsubpd1:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vhsubpd %ymm1, %ymm0, %ymm0
|
|
; AVX-NEXT: retq
|
|
%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
%r = fsub <4 x double> %a, %b
|
|
ret <4 x double> %r
|
|
}
|
|
|
|
define <2 x float> @haddps_v2f32(<4 x float> %v0) {
|
|
; SSE3-LABEL: haddps_v2f32:
|
|
; SSE3: # BB#0:
|
|
; SSE3-NEXT: haddps %xmm0, %xmm0
|
|
; SSE3-NEXT: retq
|
|
;
|
|
; AVX-LABEL: haddps_v2f32:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%v0.0 = extractelement <4 x float> %v0, i32 0
|
|
%v0.1 = extractelement <4 x float> %v0, i32 1
|
|
%v0.2 = extractelement <4 x float> %v0, i32 2
|
|
%v0.3 = extractelement <4 x float> %v0, i32 3
|
|
%op0 = fadd float %v0.0, %v0.1
|
|
%op1 = fadd float %v0.2, %v0.3
|
|
%res0 = insertelement <2 x float> undef, float %op0, i32 0
|
|
%res1 = insertelement <2 x float> %res0, float %op1, i32 1
|
|
ret <2 x float> %res1
|
|
}
|
|
|