forked from OSchip/llvm-project
1507 lines
55 KiB
C++
1507 lines
55 KiB
C++
//===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LanaiTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "LanaiISelLowering.h"
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#include "Lanai.h"
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#include "LanaiCondCode.h"
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#include "LanaiMachineFunctionInfo.h"
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#include "LanaiSubtarget.h"
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#include "LanaiTargetObjectFile.h"
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#include "MCTargetDesc/LanaiBaseInfo.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RuntimeLibcalls.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/KnownBits.h"
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#include "llvm/Support/MachineValueType.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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#include <cmath>
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#include <cstdint>
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#include <cstdlib>
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#include <utility>
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#define DEBUG_TYPE "lanai-lower"
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using namespace llvm;
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// Limit on number of instructions the lowered multiplication may have before a
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// call to the library function should be generated instead. The threshold is
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// currently set to 14 as this was the smallest threshold that resulted in all
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// constant multiplications being lowered. A threshold of 5 covered all cases
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// except for one multiplication which required 14. mulsi3 requires 16
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// instructions (including the prologue and epilogue but excluding instructions
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// at call site). Until we can inline mulsi3, generating at most 14 instructions
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// will be faster than invoking mulsi3.
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static cl::opt<int> LanaiLowerConstantMulThreshold(
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"lanai-constant-mul-threshold", cl::Hidden,
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cl::desc("Maximum number of instruction to generate when lowering constant "
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"multiplication instead of calling library function [default=14]"),
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cl::init(14));
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LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
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const LanaiSubtarget &STI)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
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// Compute derived properties from the register classes
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TRI = STI.getRegisterInfo();
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computeRegisterProperties(TRI);
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setStackPointerRegisterToSaveRestore(Lanai::SP);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::Other, Expand);
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::MUL, MVT::i32, Custom);
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setOperationAction(ISD::MULHU, MVT::i32, Expand);
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setOperationAction(ISD::MULHS, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Legal);
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setOperationAction(ISD::CTLZ, MVT::i32, Legal);
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setOperationAction(ISD::CTTZ, MVT::i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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// Extended load operations for i1 types must be promoted
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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}
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::SUB);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::XOR);
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// Function alignments
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setMinFunctionAlignment(Align(4));
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setPrefFunctionAlignment(Align(4));
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setJumpIsExpensive(true);
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// TODO: Setting the minimum jump table entries needed before a
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// switch is transformed to a jump table to 100 to avoid creating jump tables
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// as this was causing bad performance compared to a large group of if
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// statements. Re-evaluate this on new benchmarks.
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setMinimumJumpTableEntries(100);
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// Use fast calling convention for library functions.
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for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
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setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
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}
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MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
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MaxStoresPerMemsetOptSize = 8;
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MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
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MaxStoresPerMemcpyOptSize = 8;
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MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
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MaxStoresPerMemmoveOptSize = 8;
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// Booleans always contain 0 or 1.
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setBooleanContents(ZeroOrOneBooleanContent);
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}
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SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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case ISD::MUL:
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return LowerMUL(Op, DAG);
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case ISD::BR_CC:
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return LowerBR_CC(Op, DAG);
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case ISD::ConstantPool:
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return LowerConstantPool(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::BlockAddress:
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return LowerBlockAddress(Op, DAG);
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case ISD::JumpTable:
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return LowerJumpTable(Op, DAG);
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case ISD::SELECT_CC:
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return LowerSELECT_CC(Op, DAG);
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case ISD::SETCC:
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return LowerSETCC(Op, DAG);
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case ISD::SHL_PARTS:
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return LowerSHL_PARTS(Op, DAG);
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case ISD::SRL_PARTS:
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return LowerSRL_PARTS(Op, DAG);
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case ISD::VASTART:
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return LowerVASTART(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC:
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return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::RETURNADDR:
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return LowerRETURNADDR(Op, DAG);
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case ISD::FRAMEADDR:
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return LowerFRAMEADDR(Op, DAG);
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default:
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llvm_unreachable("unimplemented operand");
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}
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}
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//===----------------------------------------------------------------------===//
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// Lanai Inline Assembly Support
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//===----------------------------------------------------------------------===//
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Register LanaiTargetLowering::getRegisterByName(
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const char *RegName, LLT /*VT*/,
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const MachineFunction & /*MF*/) const {
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// Only unallocatable registers should be matched here.
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Register Reg = StringSwitch<unsigned>(RegName)
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.Case("pc", Lanai::PC)
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.Case("sp", Lanai::SP)
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.Case("fp", Lanai::FP)
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.Case("rr1", Lanai::RR1)
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.Case("r10", Lanai::R10)
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.Case("rr2", Lanai::RR2)
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.Case("r11", Lanai::R11)
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.Case("rca", Lanai::RCA)
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.Default(0);
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if (Reg)
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return Reg;
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report_fatal_error("Invalid register name global variable");
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}
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std::pair<unsigned, const TargetRegisterClass *>
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LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint,
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MVT VT) const {
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if (Constraint.size() == 1)
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// GCC Constraint Letters
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switch (Constraint[0]) {
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case 'r': // GENERAL_REGS
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return std::make_pair(0U, &Lanai::GPRRegClass);
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default:
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break;
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}
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return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
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}
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// Examine constraint type and operand type and determine a weight value.
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// This object must already have been set up with the operand type
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// and the current alternative constraint selected.
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TargetLowering::ConstraintWeight
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LanaiTargetLowering::getSingleConstraintMatchWeight(
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AsmOperandInfo &Info, const char *Constraint) const {
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ConstraintWeight Weight = CW_Invalid;
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Value *CallOperandVal = Info.CallOperandVal;
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// If we don't have a value, we can't do a match,
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// but allow it at the lowest weight.
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if (CallOperandVal == nullptr)
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return CW_Default;
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// Look at the constraint type.
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switch (*Constraint) {
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case 'I': // signed 16 bit immediate
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case 'J': // integer zero
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case 'K': // unsigned 16 bit immediate
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case 'L': // immediate in the range 0 to 31
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case 'M': // signed 32 bit immediate where lower 16 bits are 0
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case 'N': // signed 26 bit immediate
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case 'O': // integer zero
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if (isa<ConstantInt>(CallOperandVal))
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Weight = CW_Constant;
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break;
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default:
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Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
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break;
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}
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return Weight;
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}
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// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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// vector. If it is invalid, don't add anything to Ops.
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void LanaiTargetLowering::LowerAsmOperandForConstraint(
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SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const {
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SDValue Result(nullptr, 0);
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// Only support length 1 constraints for now.
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if (Constraint.length() > 1)
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return;
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char ConstraintLetter = Constraint[0];
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switch (ConstraintLetter) {
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case 'I': // Signed 16 bit constant
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// If this fails, the parent routine will give an error
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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if (isInt<16>(C->getSExtValue())) {
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Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
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Op.getValueType());
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break;
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}
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}
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return;
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case 'J': // integer zero
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case 'O':
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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if (C->getZExtValue() == 0) {
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Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
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break;
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}
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}
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return;
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case 'K': // unsigned 16 bit immediate
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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if (isUInt<16>(C->getZExtValue())) {
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Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
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Op.getValueType());
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break;
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}
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}
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return;
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case 'L': // immediate in the range 0 to 31
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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if (C->getZExtValue() <= 31) {
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Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
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Op.getValueType());
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break;
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}
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}
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return;
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case 'M': // signed 32 bit immediate where lower 16 bits are 0
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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int64_t Val = C->getSExtValue();
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if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
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Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
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break;
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}
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}
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return;
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case 'N': // signed 26 bit immediate
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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int64_t Val = C->getSExtValue();
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if ((Val >= -33554432) && (Val <= 33554431)) {
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Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
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break;
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}
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}
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return;
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default:
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break; // This will fall through to the generic implementation
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}
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if (Result.getNode()) {
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Ops.push_back(Result);
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return;
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}
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TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "LanaiGenCallingConv.inc"
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static unsigned NumFixedArgs;
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static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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// Handle fixed arguments with default CC.
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// Note: Both the default and fast CC handle VarArg the same and hence the
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// calling convention of the function is not considered here.
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if (ValNo < NumFixedArgs) {
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return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
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}
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// Promote i8/i16 args to i32
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if (LocVT == MVT::i8 || LocVT == MVT::i16) {
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LocVT = MVT::i32;
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if (ArgFlags.isSExt())
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LocInfo = CCValAssign::SExt;
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else if (ArgFlags.isZExt())
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LocInfo = CCValAssign::ZExt;
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else
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LocInfo = CCValAssign::AExt;
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}
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// VarArgs get passed on stack
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unsigned Offset = State.AllocateStack(4, Align(4));
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return false;
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}
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SDValue LanaiTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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switch (CallConv) {
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case CallingConv::C:
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case CallingConv::Fast:
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return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
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default:
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report_fatal_error("Unsupported calling convention");
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}
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}
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SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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SDLoc &DL = CLI.DL;
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SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
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SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
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SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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bool &IsTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool IsVarArg = CLI.IsVarArg;
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// Lanai target does not yet support tail call optimization.
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IsTailCall = false;
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switch (CallConv) {
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
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OutVals, Ins, DL, DAG, InVals);
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default:
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report_fatal_error("Unsupported calling convention");
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}
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}
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// LowerCCCArguments - transform physical registers into virtual registers and
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// generate load operations for arguments places on the stack.
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SDValue LanaiTargetLowering::LowerCCCArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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if (CallConv == CallingConv::Fast) {
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CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
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} else {
|
|
CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
|
|
}
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
CCValAssign &VA = ArgLocs[i];
|
|
if (VA.isRegLoc()) {
|
|
// Arguments passed in registers
|
|
EVT RegVT = VA.getLocVT();
|
|
switch (RegVT.getSimpleVT().SimpleTy) {
|
|
case MVT::i32: {
|
|
Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
|
|
RegInfo.addLiveIn(VA.getLocReg(), VReg);
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
|
|
|
|
// If this is an 8/16-bit value, it is really passed promoted to 32
|
|
// bits. Insert an assert[sz]ext to capture this, then truncate to the
|
|
// right size.
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
|
|
DAG.getValueType(VA.getValVT()));
|
|
|
|
if (VA.getLocInfo() != CCValAssign::Full)
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
|
|
|
|
InVals.push_back(ArgValue);
|
|
break;
|
|
}
|
|
default:
|
|
LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
|
|
<< RegVT.getEVTString() << "\n");
|
|
llvm_unreachable("unhandled argument type");
|
|
}
|
|
} else {
|
|
// Sanity check
|
|
assert(VA.isMemLoc());
|
|
// Load the argument to a virtual register
|
|
unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
|
|
// Check that the argument fits in stack slot
|
|
if (ObjSize > 4) {
|
|
errs() << "LowerFormalArguments Unhandled argument type: "
|
|
<< EVT(VA.getLocVT()).getEVTString() << "\n";
|
|
}
|
|
// Create the frame index object for this incoming parameter...
|
|
int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
|
|
|
|
// Create the SelectionDAG nodes corresponding to a load
|
|
// from this parameter
|
|
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
InVals.push_back(DAG.getLoad(
|
|
VA.getLocVT(), DL, Chain, FIN,
|
|
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
|
|
}
|
|
}
|
|
|
|
// The Lanai ABI for returning structs by value requires that we copy
|
|
// the sret argument into rv for the return. Save the argument into
|
|
// a virtual register so that we can access it from the return points.
|
|
if (MF.getFunction().hasStructRetAttr()) {
|
|
unsigned Reg = LanaiMFI->getSRetReturnReg();
|
|
if (!Reg) {
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
|
|
LanaiMFI->setSRetReturnReg(Reg);
|
|
}
|
|
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
|
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
|
|
}
|
|
|
|
if (IsVarArg) {
|
|
// Record the frame index of the first variable argument
|
|
// which is a value necessary to VASTART.
|
|
int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
|
|
LanaiMFI->setVarArgsFrameIndex(FI);
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
SDValue
|
|
LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
|
|
bool IsVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SDLoc &DL, SelectionDAG &DAG) const {
|
|
// CCValAssign - represent the assignment of the return value to a location
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
|
|
// CCState - Info about the registers and stack slot.
|
|
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
|
|
*DAG.getContext());
|
|
|
|
// Analize return values.
|
|
CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
|
|
|
|
SDValue Flag;
|
|
SmallVector<SDValue, 4> RetOps(1, Chain);
|
|
|
|
// Copy the result values into the output registers.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
|
|
|
|
// Guarantee that all emitted copies are stuck together with flags.
|
|
Flag = Chain.getValue(1);
|
|
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
|
|
}
|
|
|
|
// The Lanai ABI for returning structs by value requires that we copy
|
|
// the sret argument into rv for the return. We saved the argument into
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
// and into rv.
|
|
if (DAG.getMachineFunction().getFunction().hasStructRetAttr()) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo<LanaiMachineFunctionInfo>();
|
|
unsigned Reg = LanaiMFI->getSRetReturnReg();
|
|
assert(Reg &&
|
|
"SRetReturnReg should have been set in LowerFormalArguments().");
|
|
SDValue Val =
|
|
DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
|
|
|
|
Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
|
|
Flag = Chain.getValue(1);
|
|
RetOps.push_back(
|
|
DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
|
|
}
|
|
|
|
RetOps[0] = Chain; // Update chain
|
|
|
|
unsigned Opc = LanaiISD::RET_FLAG;
|
|
if (Flag.getNode())
|
|
RetOps.push_back(Flag);
|
|
|
|
// Return Void
|
|
return DAG.getNode(Opc, DL, MVT::Other,
|
|
ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
|
|
}
|
|
|
|
// LowerCCCCallTo - functions arguments are copied from virtual regs to
|
|
// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
|
|
SDValue LanaiTargetLowering::LowerCCCCallTo(
|
|
SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
|
|
bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
|
|
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
|
|
*DAG.getContext());
|
|
GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
|
|
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
NumFixedArgs = 0;
|
|
if (IsVarArg && G) {
|
|
const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
|
|
if (CalleeFn)
|
|
NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
|
|
}
|
|
if (NumFixedArgs)
|
|
CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
|
|
else {
|
|
if (CallConv == CallingConv::Fast)
|
|
CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
|
|
else
|
|
CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
|
|
}
|
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
|
|
|
// Create local copies for byval args.
|
|
SmallVector<SDValue, 8> ByValArgs;
|
|
for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
|
|
ISD::ArgFlagsTy Flags = Outs[I].Flags;
|
|
if (!Flags.isByVal())
|
|
continue;
|
|
|
|
SDValue Arg = OutVals[I];
|
|
unsigned Size = Flags.getByValSize();
|
|
Align Alignment = Flags.getNonZeroByValAlign();
|
|
|
|
int FI = MFI.CreateStackObject(Size, Alignment, false);
|
|
SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
|
|
SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
|
|
|
|
Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
|
|
/*IsVolatile=*/false,
|
|
/*AlwaysInline=*/false,
|
|
/*isTailCall=*/false, MachinePointerInfo(),
|
|
MachinePointerInfo());
|
|
ByValArgs.push_back(FIPtr);
|
|
}
|
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
|
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
|
|
SmallVector<SDValue, 12> MemOpChains;
|
|
SDValue StackPtr;
|
|
|
|
// Walk the register/memloc assignments, inserting copies/loads.
|
|
for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
|
|
CCValAssign &VA = ArgLocs[I];
|
|
SDValue Arg = OutVals[I];
|
|
ISD::ArgFlagsTy Flags = Outs[I].Flags;
|
|
|
|
// Promote the value if needed.
|
|
switch (VA.getLocInfo()) {
|
|
case CCValAssign::Full:
|
|
break;
|
|
case CCValAssign::SExt:
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
|
|
break;
|
|
case CCValAssign::ZExt:
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
|
|
break;
|
|
case CCValAssign::AExt:
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
|
|
break;
|
|
default:
|
|
llvm_unreachable("Unknown loc info!");
|
|
}
|
|
|
|
// Use local copy if it is a byval arg.
|
|
if (Flags.isByVal())
|
|
Arg = ByValArgs[J++];
|
|
|
|
// Arguments that can be passed on register must be kept at RegsToPass
|
|
// vector
|
|
if (VA.isRegLoc()) {
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
|
} else {
|
|
assert(VA.isMemLoc());
|
|
|
|
if (StackPtr.getNode() == nullptr)
|
|
StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
|
|
getPointerTy(DAG.getDataLayout()));
|
|
|
|
SDValue PtrOff =
|
|
DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
|
|
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
|
|
|
|
MemOpChains.push_back(
|
|
DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
|
|
}
|
|
}
|
|
|
|
// Transform all store nodes into one single node because all store nodes are
|
|
// independent of each other.
|
|
if (!MemOpChains.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
|
|
ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
|
|
|
|
SDValue InFlag;
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain and
|
|
// flag operands which copy the outgoing args into registers. The InFlag in
|
|
// necessary since all emitted instructions must be stuck together.
|
|
for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
|
|
Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
|
|
RegsToPass[I].second, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
// Likewise ExternalSymbol -> TargetExternalSymbol.
|
|
uint8_t OpFlag = LanaiII::MO_NO_FLAG;
|
|
if (G) {
|
|
Callee = DAG.getTargetGlobalAddress(
|
|
G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
|
|
} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
|
|
Callee = DAG.getTargetExternalSymbol(
|
|
E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
|
|
}
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Callee);
|
|
|
|
// Add a register mask operand representing the call-preserved registers.
|
|
// TODO: Should return-twice functions be handled?
|
|
const uint32_t *Mask =
|
|
TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
|
|
assert(Mask && "Missing call preserved mask for calling convention");
|
|
Ops.push_back(DAG.getRegisterMask(Mask));
|
|
|
|
// Add argument registers to the end of the list so that they are
|
|
// known live into the call.
|
|
for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
|
|
Ops.push_back(DAG.getRegister(RegsToPass[I].first,
|
|
RegsToPass[I].second.getValueType()));
|
|
|
|
if (InFlag.getNode())
|
|
Ops.push_back(InFlag);
|
|
|
|
Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
|
|
ArrayRef<SDValue>(&Ops[0], Ops.size()));
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Create the CALLSEQ_END node.
|
|
Chain = DAG.getCALLSEQ_END(
|
|
Chain,
|
|
DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
|
|
DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
|
|
DL);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
// return.
|
|
return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
|
|
InVals);
|
|
}
|
|
|
|
// LowerCallResult - Lower the result values of a call into the
|
|
// appropriate copies out of appropriate physical registers.
|
|
SDValue LanaiTargetLowering::LowerCallResult(
|
|
SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
|
|
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
|
|
// Assign locations to each value returned by this call.
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
|
|
*DAG.getContext());
|
|
|
|
CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
for (unsigned I = 0; I != RVLocs.size(); ++I) {
|
|
Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
|
|
RVLocs[I].getValVT(), InFlag)
|
|
.getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
InVals.push_back(Chain.getValue(0));
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Custom Lowerings
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL,
|
|
SDValue &RHS, SelectionDAG &DAG) {
|
|
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
|
|
|
|
// For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
|
|
// SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
|
|
// and Lanai only supports integer comparisons, so only provide definitions
|
|
// for them.
|
|
switch (SetCCOpcode) {
|
|
case ISD::SETEQ:
|
|
return LPCC::ICC_EQ;
|
|
case ISD::SETGT:
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
|
|
if (RHSC->getZExtValue() == 0xFFFFFFFF) {
|
|
// X > -1 -> X >= 0 -> is_plus(X)
|
|
RHS = DAG.getConstant(0, DL, RHS.getValueType());
|
|
return LPCC::ICC_PL;
|
|
}
|
|
return LPCC::ICC_GT;
|
|
case ISD::SETUGT:
|
|
return LPCC::ICC_UGT;
|
|
case ISD::SETLT:
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
|
|
if (RHSC->getZExtValue() == 0)
|
|
// X < 0 -> is_minus(X)
|
|
return LPCC::ICC_MI;
|
|
return LPCC::ICC_LT;
|
|
case ISD::SETULT:
|
|
return LPCC::ICC_ULT;
|
|
case ISD::SETLE:
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
|
|
if (RHSC->getZExtValue() == 0xFFFFFFFF) {
|
|
// X <= -1 -> X < 0 -> is_minus(X)
|
|
RHS = DAG.getConstant(0, DL, RHS.getValueType());
|
|
return LPCC::ICC_MI;
|
|
}
|
|
return LPCC::ICC_LE;
|
|
case ISD::SETULE:
|
|
return LPCC::ICC_ULE;
|
|
case ISD::SETGE:
|
|
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
|
|
if (RHSC->getZExtValue() == 0)
|
|
// X >= 0 -> is_plus(X)
|
|
return LPCC::ICC_PL;
|
|
return LPCC::ICC_GE;
|
|
case ISD::SETUGE:
|
|
return LPCC::ICC_UGE;
|
|
case ISD::SETNE:
|
|
return LPCC::ICC_NE;
|
|
case ISD::SETONE:
|
|
case ISD::SETUNE:
|
|
case ISD::SETOGE:
|
|
case ISD::SETOLE:
|
|
case ISD::SETOLT:
|
|
case ISD::SETOGT:
|
|
case ISD::SETOEQ:
|
|
case ISD::SETUEQ:
|
|
case ISD::SETO:
|
|
case ISD::SETUO:
|
|
llvm_unreachable("Unsupported comparison.");
|
|
default:
|
|
llvm_unreachable("Unknown integer condition code!");
|
|
}
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Cond = Op.getOperand(1);
|
|
SDValue LHS = Op.getOperand(2);
|
|
SDValue RHS = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
SDLoc DL(Op);
|
|
|
|
LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
|
|
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
|
|
SDValue Flag =
|
|
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
|
|
|
|
return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
|
|
TargetCC, Flag);
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
|
|
EVT VT = Op->getValueType(0);
|
|
if (VT != MVT::i32)
|
|
return SDValue();
|
|
|
|
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
|
|
if (!C)
|
|
return SDValue();
|
|
|
|
int64_t MulAmt = C->getSExtValue();
|
|
int32_t HighestOne = -1;
|
|
uint32_t NonzeroEntries = 0;
|
|
int SignedDigit[32] = {0};
|
|
|
|
// Convert to non-adjacent form (NAF) signed-digit representation.
|
|
// NAF is a signed-digit form where no adjacent digits are non-zero. It is the
|
|
// minimal Hamming weight representation of a number (on average 1/3 of the
|
|
// digits will be non-zero vs 1/2 for regular binary representation). And as
|
|
// the non-zero digits will be the only digits contributing to the instruction
|
|
// count, this is desirable. The next loop converts it to NAF (following the
|
|
// approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
|
|
// choosing the non-zero coefficients such that the resulting quotient is
|
|
// divisible by 2 which will cause the next coefficient to be zero.
|
|
int64_t E = std::abs(MulAmt);
|
|
int S = (MulAmt < 0 ? -1 : 1);
|
|
int I = 0;
|
|
while (E > 0) {
|
|
int ZI = 0;
|
|
if (E % 2 == 1) {
|
|
ZI = 2 - (E % 4);
|
|
if (ZI != 0)
|
|
++NonzeroEntries;
|
|
}
|
|
SignedDigit[I] = S * ZI;
|
|
if (SignedDigit[I] == 1)
|
|
HighestOne = I;
|
|
E = (E - ZI) / 2;
|
|
++I;
|
|
}
|
|
|
|
// Compute number of instructions required. Due to differences in lowering
|
|
// between the different processors this count is not exact.
|
|
// Start by assuming a shift and a add/sub for every non-zero entry (hence
|
|
// every non-zero entry requires 1 shift and 1 add/sub except for the first
|
|
// entry).
|
|
int32_t InstrRequired = 2 * NonzeroEntries - 1;
|
|
// Correct possible over-adding due to shift by 0 (which is not emitted).
|
|
if (std::abs(MulAmt) % 2 == 1)
|
|
--InstrRequired;
|
|
// Return if the form generated would exceed the instruction threshold.
|
|
if (InstrRequired > LanaiLowerConstantMulThreshold)
|
|
return SDValue();
|
|
|
|
SDValue Res;
|
|
SDLoc DL(Op);
|
|
SDValue V = Op->getOperand(0);
|
|
|
|
// Initialize the running sum. Set the running sum to the maximal shifted
|
|
// positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
|
|
// term NAF).
|
|
if (HighestOne == -1)
|
|
Res = DAG.getConstant(0, DL, MVT::i32);
|
|
else {
|
|
Res = DAG.getNode(ISD::SHL, DL, VT, V,
|
|
DAG.getConstant(HighestOne, DL, MVT::i32));
|
|
SignedDigit[HighestOne] = 0;
|
|
}
|
|
|
|
// Assemble multiplication from shift, add, sub using NAF form and running
|
|
// sum.
|
|
for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
|
|
++I) {
|
|
if (SignedDigit[I] == 0)
|
|
continue;
|
|
|
|
// Shifted multiplicand (v<<i).
|
|
SDValue Op =
|
|
DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
|
|
if (SignedDigit[I] == 1)
|
|
Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
|
|
else if (SignedDigit[I] == -1)
|
|
Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
|
|
}
|
|
return Res;
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
SDValue Cond = Op.getOperand(2);
|
|
SDLoc DL(Op);
|
|
|
|
LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
|
|
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
|
|
SDValue Flag =
|
|
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
|
|
|
|
return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
SDValue TrueV = Op.getOperand(2);
|
|
SDValue FalseV = Op.getOperand(3);
|
|
SDValue Cond = Op.getOperand(4);
|
|
SDLoc DL(Op);
|
|
|
|
LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
|
|
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
|
|
SDValue Flag =
|
|
DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
|
return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
|
|
Flag);
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
LanaiMachineFunctionInfo *FuncInfo = MF.getInfo<LanaiMachineFunctionInfo>();
|
|
|
|
SDLoc DL(Op);
|
|
SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
|
|
getPointerTy(DAG.getDataLayout()));
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
|
|
MachinePointerInfo(SV));
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue Size = Op.getOperand(1);
|
|
SDLoc DL(Op);
|
|
|
|
Register SPReg = getStackPointerRegisterToSaveRestore();
|
|
|
|
// Get a reference to the stack pointer.
|
|
SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
|
|
|
|
// Subtract the dynamic size from the actual stack size to
|
|
// obtain the new stack size.
|
|
SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
|
|
|
|
// For Lanai, the outgoing memory arguments area should be on top of the
|
|
// alloca area on the stack i.e., the outgoing memory arguments should be
|
|
// at a lower address than the alloca area. Move the alloca area down the
|
|
// stack by adding back the space reserved for outgoing arguments to SP
|
|
// here.
|
|
//
|
|
// We do not know what the size of the outgoing args is at this point.
|
|
// So, we add a pseudo instruction ADJDYNALLOC that will adjust the
|
|
// stack pointer. We replace this instruction with on that has the correct,
|
|
// known offset in emitPrologue().
|
|
SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
|
|
|
|
// The Sub result contains the new stack start address, so it
|
|
// must be placed in the stack pointer register.
|
|
SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
|
|
|
|
SDValue Ops[2] = {ArgAdjust, CopyChain};
|
|
return DAG.getMergeValues(Ops, DL);
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerRETURNADDR(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
MFI.setReturnAddressIsTaken(true);
|
|
|
|
EVT VT = Op.getValueType();
|
|
SDLoc DL(Op);
|
|
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
|
if (Depth) {
|
|
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
|
|
const unsigned Offset = -4;
|
|
SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
|
|
DAG.getIntPtrConstant(Offset, DL));
|
|
return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
|
|
}
|
|
|
|
// Return the link register, which contains the return address.
|
|
// Mark it an implicit live-in.
|
|
unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
|
|
return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerFRAMEADDR(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
|
|
MFI.setFrameAddressIsTaken(true);
|
|
|
|
EVT VT = Op.getValueType();
|
|
SDLoc DL(Op);
|
|
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
|
|
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
|
while (Depth--) {
|
|
const unsigned Offset = -8;
|
|
SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
|
|
DAG.getIntPtrConstant(Offset, DL));
|
|
FrameAddr =
|
|
DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
|
|
}
|
|
return FrameAddr;
|
|
}
|
|
|
|
const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
case LanaiISD::ADJDYNALLOC:
|
|
return "LanaiISD::ADJDYNALLOC";
|
|
case LanaiISD::RET_FLAG:
|
|
return "LanaiISD::RET_FLAG";
|
|
case LanaiISD::CALL:
|
|
return "LanaiISD::CALL";
|
|
case LanaiISD::SELECT_CC:
|
|
return "LanaiISD::SELECT_CC";
|
|
case LanaiISD::SETCC:
|
|
return "LanaiISD::SETCC";
|
|
case LanaiISD::SUBBF:
|
|
return "LanaiISD::SUBBF";
|
|
case LanaiISD::SET_FLAG:
|
|
return "LanaiISD::SET_FLAG";
|
|
case LanaiISD::BR_CC:
|
|
return "LanaiISD::BR_CC";
|
|
case LanaiISD::Wrapper:
|
|
return "LanaiISD::Wrapper";
|
|
case LanaiISD::HI:
|
|
return "LanaiISD::HI";
|
|
case LanaiISD::LO:
|
|
return "LanaiISD::LO";
|
|
case LanaiISD::SMALL:
|
|
return "LanaiISD::SMALL";
|
|
default:
|
|
return nullptr;
|
|
}
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerConstantPool(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
|
|
const Constant *C = N->getConstVal();
|
|
const LanaiTargetObjectFile *TLOF =
|
|
static_cast<const LanaiTargetObjectFile *>(
|
|
getTargetMachine().getObjFileLowering());
|
|
|
|
// If the code model is small or constant will be placed in the small section,
|
|
// then assume address will fit in 21-bits.
|
|
if (getTargetMachine().getCodeModel() == CodeModel::Small ||
|
|
TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
|
|
SDValue Small = DAG.getTargetConstantPool(
|
|
C, MVT::i32, N->getAlign(), N->getOffset(), LanaiII::MO_NO_FLAG);
|
|
return DAG.getNode(ISD::OR, DL, MVT::i32,
|
|
DAG.getRegister(Lanai::R0, MVT::i32),
|
|
DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
|
|
} else {
|
|
uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
|
|
uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
|
|
|
|
SDValue Hi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
|
|
N->getOffset(), OpFlagHi);
|
|
SDValue Lo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlign(),
|
|
N->getOffset(), OpFlagLo);
|
|
Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
|
|
Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
|
|
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
|
|
|
|
const LanaiTargetObjectFile *TLOF =
|
|
static_cast<const LanaiTargetObjectFile *>(
|
|
getTargetMachine().getObjFileLowering());
|
|
|
|
// If the code model is small or global variable will be placed in the small
|
|
// section, then assume address will fit in 21-bits.
|
|
const GlobalObject *GO = GV->getBaseObject();
|
|
if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
|
|
SDValue Small = DAG.getTargetGlobalAddress(
|
|
GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
|
|
return DAG.getNode(ISD::OR, DL, MVT::i32,
|
|
DAG.getRegister(Lanai::R0, MVT::i32),
|
|
DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
|
|
} else {
|
|
uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
|
|
uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
|
|
|
|
// Create the TargetGlobalAddress node, folding in the constant offset.
|
|
SDValue Hi = DAG.getTargetGlobalAddress(
|
|
GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
|
|
SDValue Lo = DAG.getTargetGlobalAddress(
|
|
GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
|
|
Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
|
|
Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
|
|
return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
|
|
}
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerBlockAddress(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
|
|
|
|
uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
|
|
uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
|
|
|
|
SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
|
|
SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
|
|
Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
|
|
Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
|
|
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
|
|
return Result;
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerJumpTable(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
|
|
// If the code model is small assume address will fit in 21-bits.
|
|
if (getTargetMachine().getCodeModel() == CodeModel::Small) {
|
|
SDValue Small = DAG.getTargetJumpTable(
|
|
JT->getIndex(), getPointerTy(DAG.getDataLayout()), LanaiII::MO_NO_FLAG);
|
|
return DAG.getNode(ISD::OR, DL, MVT::i32,
|
|
DAG.getRegister(Lanai::R0, MVT::i32),
|
|
DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
|
|
} else {
|
|
uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
|
|
uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
|
|
|
|
SDValue Hi = DAG.getTargetJumpTable(
|
|
JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
|
|
SDValue Lo = DAG.getTargetJumpTable(
|
|
JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
|
|
Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
|
|
Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
|
|
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerSHL_PARTS(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
EVT VT = Op.getValueType();
|
|
unsigned VTBits = VT.getSizeInBits();
|
|
SDLoc dl(Op);
|
|
assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
|
|
SDValue ShOpLo = Op.getOperand(0);
|
|
SDValue ShOpHi = Op.getOperand(1);
|
|
SDValue ShAmt = Op.getOperand(2);
|
|
|
|
// Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
|
|
// LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
|
|
// HiBitsForHi = ShOpHi << ShAmt
|
|
// Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
|
|
// Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
|
|
// return (Hi << 32) | Lo;
|
|
|
|
SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
|
|
DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
|
|
SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
|
|
|
|
// If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
|
|
// wanted 0, so CSEL it directly.
|
|
SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
|
|
SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
|
|
LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
|
|
|
|
SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
|
|
DAG.getConstant(VTBits, dl, MVT::i32));
|
|
SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
|
|
SDValue HiForNormalShift =
|
|
DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
|
|
|
|
SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
|
|
|
|
SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
|
|
SDValue Hi =
|
|
DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
|
|
|
|
// Lanai shifts of larger than register sizes are wrapped rather than
|
|
// clamped, so we can't just emit "lo << b" if b is too big.
|
|
SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
|
|
SDValue Lo = DAG.getSelect(
|
|
dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
|
|
|
|
SDValue Ops[2] = {Lo, Hi};
|
|
return DAG.getMergeValues(Ops, dl);
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::LowerSRL_PARTS(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
MVT VT = Op.getSimpleValueType();
|
|
unsigned VTBits = VT.getSizeInBits();
|
|
SDLoc dl(Op);
|
|
SDValue ShOpLo = Op.getOperand(0);
|
|
SDValue ShOpHi = Op.getOperand(1);
|
|
SDValue ShAmt = Op.getOperand(2);
|
|
|
|
// Performs the following for a >> b:
|
|
// unsigned r_high = a_high >> b;
|
|
// r_high = (32 - b <= 0) ? 0 : r_high;
|
|
//
|
|
// unsigned r_low = a_low >> b;
|
|
// r_low = (32 - b <= 0) ? r_high : r_low;
|
|
// r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
|
|
// return (unsigned long long)r_high << 32 | r_low;
|
|
// Note: This takes advantage of Lanai's shift behavior to avoid needing to
|
|
// mask the shift amount.
|
|
|
|
SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
|
|
SDValue NegatedPlus32 = DAG.getNode(
|
|
ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
|
|
SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
|
|
|
|
SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
|
|
Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
|
|
|
|
SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
|
|
Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
|
|
SDValue CarryBits =
|
|
DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
|
|
SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
|
|
Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
|
|
DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
|
|
|
|
SDValue Ops[2] = {Lo, Hi};
|
|
return DAG.getMergeValues(Ops, dl);
|
|
}
|
|
|
|
// Helper function that checks if N is a null or all ones constant.
|
|
static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
|
|
return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
|
|
}
|
|
|
|
// Return true if N is conditionally 0 or all ones.
|
|
// Detects these expressions where cc is an i1 value:
|
|
//
|
|
// (select cc 0, y) [AllOnes=0]
|
|
// (select cc y, 0) [AllOnes=0]
|
|
// (zext cc) [AllOnes=0]
|
|
// (sext cc) [AllOnes=0/1]
|
|
// (select cc -1, y) [AllOnes=1]
|
|
// (select cc y, -1) [AllOnes=1]
|
|
//
|
|
// * AllOnes determines whether to check for an all zero (AllOnes false) or an
|
|
// all ones operand (AllOnes true).
|
|
// * Invert is set when N is the all zero/ones constant when CC is false.
|
|
// * OtherOp is set to the alternative value of N.
|
|
//
|
|
// For example, for (select cc X, Y) and AllOnes = 0 if:
|
|
// * X = 0, Invert = False and OtherOp = Y
|
|
// * Y = 0, Invert = True and OtherOp = X
|
|
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
|
|
bool &Invert, SDValue &OtherOp,
|
|
SelectionDAG &DAG) {
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
return false;
|
|
case ISD::SELECT: {
|
|
CC = N->getOperand(0);
|
|
SDValue N1 = N->getOperand(1);
|
|
SDValue N2 = N->getOperand(2);
|
|
if (isZeroOrAllOnes(N1, AllOnes)) {
|
|
Invert = false;
|
|
OtherOp = N2;
|
|
return true;
|
|
}
|
|
if (isZeroOrAllOnes(N2, AllOnes)) {
|
|
Invert = true;
|
|
OtherOp = N1;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
case ISD::ZERO_EXTEND: {
|
|
// (zext cc) can never be the all ones value.
|
|
if (AllOnes)
|
|
return false;
|
|
CC = N->getOperand(0);
|
|
if (CC.getValueType() != MVT::i1)
|
|
return false;
|
|
SDLoc dl(N);
|
|
EVT VT = N->getValueType(0);
|
|
OtherOp = DAG.getConstant(1, dl, VT);
|
|
Invert = true;
|
|
return true;
|
|
}
|
|
case ISD::SIGN_EXTEND: {
|
|
CC = N->getOperand(0);
|
|
if (CC.getValueType() != MVT::i1)
|
|
return false;
|
|
SDLoc dl(N);
|
|
EVT VT = N->getValueType(0);
|
|
Invert = !AllOnes;
|
|
if (AllOnes)
|
|
// When looking for an AllOnes constant, N is an sext, and the 'other'
|
|
// value is 0.
|
|
OtherOp = DAG.getConstant(0, dl, VT);
|
|
else
|
|
OtherOp =
|
|
DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Combine a constant select operand into its use:
|
|
//
|
|
// (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
|
|
// (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
|
|
// (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
|
|
// (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
|
|
// (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
|
|
//
|
|
// The transform is rejected if the select doesn't have a constant operand that
|
|
// is null, or all ones when AllOnes is set.
|
|
//
|
|
// Also recognize sext/zext from i1:
|
|
//
|
|
// (add (zext cc), x) -> (select cc (add x, 1), x)
|
|
// (add (sext cc), x) -> (select cc (add x, -1), x)
|
|
//
|
|
// These transformations eventually create predicated instructions.
|
|
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
bool AllOnes) {
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
EVT VT = N->getValueType(0);
|
|
SDValue NonConstantVal;
|
|
SDValue CCOp;
|
|
bool SwapSelectOps;
|
|
if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
|
|
NonConstantVal, DAG))
|
|
return SDValue();
|
|
|
|
// Slct is now know to be the desired identity constant when CC is true.
|
|
SDValue TrueVal = OtherOp;
|
|
SDValue FalseVal =
|
|
DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
|
|
// Unless SwapSelectOps says CC should be false.
|
|
if (SwapSelectOps)
|
|
std::swap(TrueVal, FalseVal);
|
|
|
|
return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
|
|
}
|
|
|
|
// Attempt combineSelectAndUse on each operand of a commutative operator N.
|
|
static SDValue
|
|
combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
|
|
bool AllOnes) {
|
|
SDValue N0 = N->getOperand(0);
|
|
SDValue N1 = N->getOperand(1);
|
|
if (N0.getNode()->hasOneUse())
|
|
if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
|
|
return Result;
|
|
if (N1.getNode()->hasOneUse())
|
|
if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
|
|
return Result;
|
|
return SDValue();
|
|
}
|
|
|
|
// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
|
|
static SDValue PerformSUBCombine(SDNode *N,
|
|
TargetLowering::DAGCombinerInfo &DCI) {
|
|
SDValue N0 = N->getOperand(0);
|
|
SDValue N1 = N->getOperand(1);
|
|
|
|
// fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
|
|
if (N1.getNode()->hasOneUse())
|
|
if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
|
|
return Result;
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
|
|
DAGCombinerInfo &DCI) const {
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
break;
|
|
case ISD::ADD:
|
|
case ISD::OR:
|
|
case ISD::XOR:
|
|
return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
|
|
case ISD::AND:
|
|
return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
|
|
case ISD::SUB:
|
|
return PerformSUBCombine(N, DCI);
|
|
}
|
|
|
|
return SDValue();
|
|
}
|
|
|
|
void LanaiTargetLowering::computeKnownBitsForTargetNode(
|
|
const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
|
|
const SelectionDAG &DAG, unsigned Depth) const {
|
|
unsigned BitWidth = Known.getBitWidth();
|
|
switch (Op.getOpcode()) {
|
|
default:
|
|
break;
|
|
case LanaiISD::SETCC:
|
|
Known = KnownBits(BitWidth);
|
|
Known.Zero.setBits(1, BitWidth);
|
|
break;
|
|
case LanaiISD::SELECT_CC:
|
|
KnownBits Known2;
|
|
Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
|
|
Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
|
|
Known = KnownBits::commonBits(Known, Known2);
|
|
break;
|
|
}
|
|
}
|