forked from OSchip/llvm-project
6afef286d9
Prior to this patch, the AVR::LDWRdPtr instruction was always lowered to
instructions of this pattern:
ld $GPR8, [PTR:XYZ]+
ld $GPR8, [PTR]+1
This has a problem; the [PTR] is incremented in-place once, but never
decremented.
Future uses of the same pointer will use the now clobbered value,
leading to the pointer being incorrect by an offset of one.
This patch modifies the expansion code of the LDWRdPtr pseudo
instruction so that the pointer variable is not silently clobbered in
future uses in the same live range.
Bug first reported by Keshav Kini.
Patch by Kaushik Phatak.
llvm-svn: 351673
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| .. | ||
| ADCWRdRr.mir | ||
| ADDWRdRr.mir | ||
| ANDIWRdK.mir | ||
| ANDWRdRr.mir | ||
| ASRWRd.mir | ||
| COMWRd.mir | ||
| CPCWRdRr.mir | ||
| CPWRdRr.mir | ||
| EORWRdRr.mir | ||
| FRMIDX.mir | ||
| INWRdA.mir | ||
| LDDWRdPtrQ-same-src-dst.mir | ||
| LDDWRdPtrQ.mir | ||
| LDDWRdYQ.mir | ||
| LDIWRdK.mir | ||
| LDSWRdK.mir | ||
| LDWRdPtr-same-src-dst.mir | ||
| LDWRdPtr.mir | ||
| LDWRdPtrPd.mir | ||
| LDWRdPtrPi.mir | ||
| LSLWRd.mir | ||
| LSRWRd.mir | ||
| ORIWRdK.mir | ||
| ORWRdRr.mir | ||
| OUTWARr.mir | ||
| POPWRd.mir | ||
| PUSHWRr.mir | ||
| SBCIWRdK.mir | ||
| SBCWRdRr.mir | ||
| SEXT.mir | ||
| STDWPtrQRr.mir | ||
| STSWKRr.mir | ||
| STWPtrPdRr.mir | ||
| STWPtrPiRr.mir | ||
| STWPtrRr.mir | ||
| SUBIWRdK.mir | ||
| SUBWRdRr.mir | ||
| ZEXT.mir | ||