llvm-project/llvm/test/CodeGen
Craig Topper ce8b3937dd [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
If we are able to compare with 0 instead of 1, we might be able
to fold the setcc into a beqz/bnez.

Often these setccs start life as an xor that gets converted to
a setcc by DAG combiner's rebuildSetcc. I looked into a detecting
(xor X, 1) and converting to (seteq X, 0) based on boolean contents
being 0/1 in rebuildSetcc instead of using computeKnownBits. It was
very perturbing to AMDGPU tests which I didn't look closely at.
It had a few changes on a couple other targets, but didn't seem
to be much if any improvement.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94730
2021-01-19 11:21:48 -08:00
..
AArch64 [GlobalISel] Combine (a[0]) | (a[1] << k1) | ...| (a[m] << kn) into a wide load 2021-01-19 10:24:27 -08:00
AMDGPU [AMDGPU] Fix test case for D94010 2021-01-19 16:46:47 +00:00
ARC
ARM [ARM][MachineOutliner] Add stack fixup feature 2021-01-19 10:59:09 +01:00
AVR
BPF [BPF] support atomic instructions 2020-12-03 07:38:00 -08:00
Generic Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
Hexagon [Hexagon] Fix segment start to adjust for gaps between segments 2021-01-19 12:49:39 -06:00
Inputs
Lanai
MIR [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
MSP430
Mips [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
NVPTX [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00
PowerPC [PowerPC] Fix the check for the instruction using FRSP/XSRSP output register 2021-01-19 09:20:03 -06:00
RISCV [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1. 2021-01-19 11:21:48 -08:00
SPARC [SPARC] Fix fp128 load/stores 2021-01-13 14:59:50 -08:00
SystemZ [SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds 2021-01-14 15:46:27 +00:00
Thumb
Thumb2 [ARM] Expand vXi1 VSELECT's 2021-01-19 17:56:50 +00:00
VE [VE] Update VELIntrinsic tests 2021-01-13 00:12:50 +09:00
WebAssembly [WebAssembly] call_indirect issues table number relocs 2021-01-19 09:32:45 +01:00
WinCFGuard
WinEH
X86 [X86] Regenerate fmin/fmax reduction tests 2021-01-19 14:28:44 +00:00
XCore [test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:47:16 -08:00
lit.local.cfg [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00