forked from OSchip/llvm-project
78 lines
2.4 KiB
LLVM
78 lines
2.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx| FileCheck %s
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; Verify that we generate a single OR instruction for a scalar, vec128, and vec256
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; FNABS(x) operation -> FNEG (FABS(x)).
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; If the FABS() result isn't used, the AND instruction should be eliminated.
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; PR20578: http://llvm.org/bugs/show_bug.cgi?id=20578
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define float @scalar_no_abs(float %a) {
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; CHECK-LABEL: scalar_no_abs:
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; CHECK: vorps
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; CHECK-NEXT: retq
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%fabs = tail call float @fabsf(float %a) #1
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%fsub = fsub float -0.0, %fabs
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ret float %fsub
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}
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define float @scalar_uses_abs(float %a) {
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; CHECK-LABEL: scalar_uses_abs:
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; CHECK-DAG: vandps
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; CHECK-DAG: vorps
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; CHECK: vmulss
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; CHECK-NEXT: retq
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%fabs = tail call float @fabsf(float %a) #1
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%fsub = fsub float -0.0, %fabs
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%fmul = fmul float %fsub, %fabs
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ret float %fmul
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}
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define <4 x float> @vector128_no_abs(<4 x float> %a) {
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; CHECK-LABEL: vector128_no_abs:
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; CHECK: vorps
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; CHECK-NEXT: retq
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%fabs = tail call <4 x float> @llvm.fabs.v4f32(< 4 x float> %a) #1
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%fsub = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
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ret <4 x float> %fsub
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}
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define <4 x float> @vector128_uses_abs(<4 x float> %a) {
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; CHECK-LABEL: vector128_uses_abs:
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; CHECK-DAG: vandps
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; CHECK-DAG: vorps
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; CHECK: vmulps
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; CHECK-NEXT: retq
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%fabs = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) #1
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%fsub = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
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%fmul = fmul <4 x float> %fsub, %fabs
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ret <4 x float> %fmul
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}
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define <8 x float> @vector256_no_abs(<8 x float> %a) {
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; CHECK-LABEL: vector256_no_abs:
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; CHECK: vorps
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; CHECK-NEXT: retq
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%fabs = tail call <8 x float> @llvm.fabs.v8f32(< 8 x float> %a) #1
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%fsub = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
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ret <8 x float> %fsub
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}
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define <8 x float> @vector256_uses_abs(<8 x float> %a) {
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; CHECK-LABEL: vector256_uses_abs:
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; CHECK-DAG: vandps
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; CHECK-DAG: vorps
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; CHECK: vmulps
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; CHECK-NEXT: retq
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%fabs = tail call <8 x float> @llvm.fabs.v8f32(<8 x float> %a) #1
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%fsub = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, %fabs
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%fmul = fmul <8 x float> %fsub, %fabs
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ret <8 x float> %fmul
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
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declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
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declare float @fabsf(float)
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attributes #1 = { readnone }
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