forked from OSchip/llvm-project
81 lines
3.8 KiB
LLVM
81 lines
3.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mattr=+avx
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; Various missing patterns causing crashes.
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; rdar://10538793
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define void @t1() nounwind {
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entry:
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br label %loop.cond
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loop.cond: ; preds = %t1.exit, %entry
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br i1 false, label %return, label %loop
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loop: ; preds = %loop.cond
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br i1 undef, label %0, label %t1.exit
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; <label>:0 ; preds = %loop
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%1 = load <16 x i32> addrspace(1)* undef, align 64
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%2 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %1, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 0, i32 0>
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store <16 x i32> %2, <16 x i32> addrspace(1)* undef, align 64
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br label %t1.exit
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t1.exit: ; preds = %0, %loop
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br label %loop.cond
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return: ; preds = %loop.cond
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ret void
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}
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define void @t2() nounwind {
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br i1 undef, label %1, label %4
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; <label>:1 ; preds = %0
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%2 = load <16 x i32> addrspace(1)* undef, align 64
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%3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 20, i32 0, i32 0, i32 0, i32 0>
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store <16 x i32> %3, <16 x i32> addrspace(1)* undef, align 64
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br label %4
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; <label>:4 ; preds = %1, %0
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ret void
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}
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define void @t3() nounwind {
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entry:
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br label %loop.cond
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loop.cond: ; preds = %t2.exit, %entry
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br i1 false, label %return, label %loop
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loop: ; preds = %loop.cond
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br i1 undef, label %0, label %t2.exit
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; <label>:0 ; preds = %loop
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%1 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 25, i32 0>
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%2 = load <16 x i32> addrspace(1)* undef, align 64
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%3 = shufflevector <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, <16 x i32> %2, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 28, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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store <16 x i32> %3, <16 x i32> addrspace(1)* undef, align 64
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br label %t2.exit
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t2.exit: ; preds = %0, %loop
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br label %loop.cond
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return: ; preds = %loop.cond
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ret void
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}
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define <3 x i64> @t4() nounwind {
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entry:
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%0 = load <2 x i64> addrspace(1)* undef, align 16
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%1 = extractelement <2 x i64> %0, i32 0
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%2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 0
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ret <3 x i64> %2
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}
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define void @t5() nounwind {
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entry:
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%0 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%1 = shufflevector <8 x i64> <i64 0, i64 0, i64 0, i64 undef, i64 undef, i64 0, i64 0, i64 0>, <8 x i64> %0, <8 x i32> <i32 0, i32 1, i32 2, i32 9, i32 8, i32 5, i32 6, i32 7>
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store <8 x i64> %1, <8 x i64> addrspace(1)* undef, align 64
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ret void
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}
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