Sanjay Patel d27a21874b [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433) ... This should fix: https://llvm.org/bugs/show_bug.cgi?id=30433 There are a couple of open questions about the codegen: 1. Should we let scalar ops be scalars and avoid vector constant loads/splats? 2. Should we have a pass to combine constants such as the inverted pair that we have here? Differential Revision: https://reviews.llvm.org/D25165 llvm-svn: 283119		2016-10-03 16:38:27 +00:00
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AArch64	[AArch64] Reduce vector insert/extract cost for Kryo	2016-02-18 18:35:45 +00:00
AMDGPU	AMDGPU: Cost model for basic integer operations	2016-03-25 01:16:40 +00:00
ARM	[TTI] The cost model should not assume vector casts get completely scalarized	2016-07-06 17:30:56 +00:00
PowerPC	[TTI] The cost model should not assume vector casts get completely scalarized	2016-07-06 17:30:56 +00:00
X86	[x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433)	2016-10-03 16:38:27 +00:00
no_info.ll	Roll forward r243250	2015-07-26 19:10:03 +00:00