llvm-project/llvm/test/CodeGen
Zi Xuan Wu 9479f6d72e [PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel
Bad machine code: Illegal virtual register for instruction

function: TestULE
basic block: %bb.0 entry (0x1000a39b158)
instruction: %2:crrc = FCMPUD %1:vsfrc, %3:f8rc
operand 1: %1:vsfrc

Fix assert about missing match between fcmp instruction and register class. 
We should use vsx related cmp instruction xvcmpudp instead of fcmpu when vsx is opened.

add -verifymachineinstrs option into related test cases to enable the verify pass.


Differential Revision: https://reviews.llvm.org/D55686

llvm-svn: 350685
2019-01-09 02:31:10 +00:00
..
AArch64 [GlobalISel] Fix choice of instruction selector for AArch64 at -O0 with -global-isel=0 2019-01-08 14:19:06 +00:00
AMDGPU RegisterCoalescer: Assume CR_Replace for SubRangeJoin 2019-01-08 23:22:18 +00:00
ARC
ARM [ARM] Add missing patterns for DSP muls 2019-01-08 10:12:36 +00:00
AVR [AVR] Update integration/blink.ll as we now generate sbi/cbi instructions. 2019-01-03 21:25:39 +00:00
BPF [BPF] Fix .BTF.ext reloc type assigment issue 2019-01-08 16:36:06 +00:00
Generic Move llc-start-stop-instance to x86 2018-12-04 18:19:08 +00:00
Hexagon [DAGCombiner] allow narrowing of add followed by truncate 2018-12-22 17:10:31 +00:00
Inputs
Lanai [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00
MIR [Dwarf/AArch64] Return address signing B key dwarf support 2018-12-21 10:45:08 +00:00
MSP430 [MSP430] Optimize srl/sra in case of A >> (8 + N) 2018-11-19 10:43:02 +00:00
Mips [MIPS GlobalISel] Select G_SELECT 2018-12-25 14:42:30 +00:00
NVPTX Python compat - print statement 2019-01-03 14:11:33 +00:00
Nios2
PowerPC [PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel 2019-01-09 02:31:10 +00:00
RISCV [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
SPARC [Sparc] Use float register for integer constrained with "f" in inline asm 2018-12-13 15:13:29 +00:00
SystemZ Pythran compat - range vs. xrange 2019-01-03 14:11:58 +00:00
Thumb [ARM] Complete the Thumb1 shift+and->shift+shift transforms. 2018-12-20 23:39:54 +00:00
Thumb2
WebAssembly [WebAssembly] Massive instruction renaming 2019-01-08 06:25:55 +00:00
WinCFGuard
WinEH
X86 [x86] add tests for PR40243; NFC 2019-01-08 19:15:21 +00:00
XCore [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00