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llvm-project/llvm/test/CodeGen/MIR
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Krzysztof Parzyszek 6a0005d1b4 Move machine-cse-physreg.mir to test/CodeGen/Thumb 
llvm-svn: 303778
 		2017-05-24 17:20:47 +00:00
..
AArch64 MIR: parse & print the atomic parts of a MachineMemOperand. 2017-02-13 22:14:08 +00:00
AMDGPU AMDGPU: Remove legacy bfe intrinsics 2017-04-03 18:08:08 +00:00
ARM [IfConversion] Keep the CFG updated incrementally in IfConvertTriangle 2017-05-12 06:28:58 +00:00
Generic Move machine-cse-physreg.mir to test/CodeGen/Thumb 2017-05-24 17:20:47 +00:00
Hexagon Move .mir tests to appropriate directories 2016-12-09 19:08:15 +00:00
Mips MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
NVPTX llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
PowerPC MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. 2016-08-24 01:32:41 +00:00
X86 Add extra operand to CALLSEQ_START to keep frame part set up previously 2017-05-09 13:35:13 +00:00
README Add README describing the intention of test/CodeGen/MIR 2016-12-09 20:16:12 +00:00

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.