forked from OSchip/llvm-project
433 lines
23 KiB
LLVM
433 lines
23 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}phi1:
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; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
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; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]]
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define amdgpu_ps void @phi1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0)
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%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
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%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32)
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%tmp24 = fptosi float %tmp22 to i32
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%tmp25 = icmp ne i32 %tmp24, 0
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br i1 %tmp25, label %ENDIF, label %ELSE
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ELSE: ; preds = %main_body
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%tmp26 = fsub float -0.000000e+00, %tmp21
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br label %ENDIF
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ENDIF: ; preds = %ELSE, %main_body
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%temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]
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%tmp27 = fadd float %temp.0, %tmp23
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
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ret void
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}
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; Make sure this program doesn't crash
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; CHECK-LABEL: {{^}}phi2:
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define amdgpu_ps void @phi2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
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%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32)
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%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 36)
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%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 40)
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%tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 48)
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%tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 52)
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%tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 56)
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%tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 64)
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%tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 68)
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%tmp30 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 72)
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%tmp31 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 76)
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%tmp32 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 80)
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%tmp33 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 84)
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%tmp34 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 88)
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%tmp35 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 92)
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%tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %arg2, i32 0
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%tmp37 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp36, !tbaa !0
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%tmp38 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg1, i32 0
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%tmp39 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp38, !tbaa !0
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%i.i = extractelement <2 x i32> %arg5, i32 0
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%j.i = extractelement <2 x i32> %arg5, i32 1
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%i.f.i = bitcast i32 %i.i to float
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%j.f.i = bitcast i32 %j.i to float
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%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1
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%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1
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%i.i19 = extractelement <2 x i32> %arg5, i32 0
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%j.i20 = extractelement <2 x i32> %arg5, i32 1
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%i.f.i21 = bitcast i32 %i.i19 to float
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%j.f.i22 = bitcast i32 %j.i20 to float
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%p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #1
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%p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #1
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%i.i13 = extractelement <2 x i32> %arg5, i32 0
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%j.i14 = extractelement <2 x i32> %arg5, i32 1
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%i.f.i15 = bitcast i32 %i.i13 to float
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%j.f.i16 = bitcast i32 %j.i14 to float
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%p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #1
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%p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #1
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%i.i7 = extractelement <2 x i32> %arg5, i32 0
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%j.i8 = extractelement <2 x i32> %arg5, i32 1
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%i.f.i9 = bitcast i32 %i.i7 to float
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%j.f.i10 = bitcast i32 %j.i8 to float
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%p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #1
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%p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #1
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%i.i1 = extractelement <2 x i32> %arg5, i32 0
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%j.i2 = extractelement <2 x i32> %arg5, i32 1
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%i.f.i3 = bitcast i32 %i.i1 to float
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%j.f.i4 = bitcast i32 %j.i2 to float
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%p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #1
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%p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #1
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%tmp45 = bitcast float %p2.i to i32
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%tmp46 = bitcast float %p2.i24 to i32
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%tmp47 = insertelement <2 x i32> undef, i32 %tmp45, i32 0
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%tmp48 = insertelement <2 x i32> %tmp47, i32 %tmp46, i32 1
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%tmp39.bc = bitcast <4 x i32> %tmp39 to <4 x i32>
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%a.bc.i = bitcast <2 x i32> %tmp48 to <2 x float>
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%tmp1 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %a.bc.i, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
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%tmp50 = extractelement <4 x float> %tmp1, i32 2
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%tmp51 = call float @llvm.fabs.f32(float %tmp50)
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%tmp52 = fmul float %p2.i18, %p2.i18
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%tmp53 = fmul float %p2.i12, %p2.i12
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%tmp54 = fadd float %tmp53, %tmp52
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%tmp55 = fmul float %p2.i6, %p2.i6
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%tmp56 = fadd float %tmp54, %tmp55
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%tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56)
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%tmp58 = fmul float %p2.i18, %tmp57
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%tmp59 = fmul float %p2.i12, %tmp57
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%tmp60 = fmul float %p2.i6, %tmp57
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%tmp61 = fmul float %tmp58, %tmp22
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%tmp62 = fmul float %tmp59, %tmp23
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%tmp63 = fadd float %tmp62, %tmp61
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%tmp64 = fmul float %tmp60, %tmp24
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%tmp65 = fadd float %tmp63, %tmp64
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%tmp66 = fsub float -0.000000e+00, %tmp25
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%tmp67 = fmul float %tmp65, %tmp51
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%tmp68 = fadd float %tmp67, %tmp66
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%tmp69 = fmul float %tmp26, %tmp68
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%tmp70 = fmul float %tmp27, %tmp68
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%tmp71 = call float @llvm.fabs.f32(float %tmp69)
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%tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71
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%tmp73 = sext i1 %tmp72 to i32
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%tmp74 = bitcast i32 %tmp73 to float
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%tmp75 = bitcast float %tmp74 to i32
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%tmp76 = icmp ne i32 %tmp75, 0
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br i1 %tmp76, label %IF, label %ENDIF
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IF: ; preds = %main_body
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%tmp77 = fsub float -0.000000e+00, %tmp69
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%tmp78 = call float @llvm.exp2.f32(float %tmp77)
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%tmp79 = fsub float -0.000000e+00, %tmp78
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%tmp80 = fadd float 1.000000e+00, %tmp79
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%tmp81 = fdiv float 1.000000e+00, %tmp69
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%tmp82 = fmul float %tmp80, %tmp81
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%tmp83 = fmul float %tmp31, %tmp82
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br label %ENDIF
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ENDIF: ; preds = %IF, %main_body
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%temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ]
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%tmp84 = call float @llvm.fabs.f32(float %tmp70)
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%tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84
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%tmp86 = sext i1 %tmp85 to i32
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%tmp87 = bitcast i32 %tmp86 to float
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%tmp88 = bitcast float %tmp87 to i32
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%tmp89 = icmp ne i32 %tmp88, 0
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br i1 %tmp89, label %IF25, label %ENDIF24
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IF25: ; preds = %ENDIF
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%tmp90 = fsub float -0.000000e+00, %tmp70
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%tmp91 = call float @llvm.exp2.f32(float %tmp90)
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%tmp92 = fsub float -0.000000e+00, %tmp91
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%tmp93 = fadd float 1.000000e+00, %tmp92
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%tmp94 = fdiv float 1.000000e+00, %tmp70
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%tmp95 = fmul float %tmp93, %tmp94
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%tmp96 = fmul float %tmp35, %tmp95
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br label %ENDIF24
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ENDIF24: ; preds = %IF25, %ENDIF
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%temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ]
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%tmp97 = fmul float %tmp28, %temp4.0
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%tmp98 = fmul float %tmp29, %temp4.0
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%tmp99 = fmul float %tmp30, %temp4.0
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%tmp100 = fmul float %tmp32, %temp8.0
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%tmp101 = fadd float %tmp100, %tmp97
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%tmp102 = fmul float %tmp33, %temp8.0
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%tmp103 = fadd float %tmp102, %tmp98
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%tmp104 = fmul float %tmp34, %temp8.0
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%tmp105 = fadd float %tmp104, %tmp99
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%tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21)
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%tmp107 = fsub float -0.000000e+00, %tmp101
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%tmp108 = fmul float %tmp107, %tmp106
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%tmp109 = fsub float -0.000000e+00, %tmp103
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%tmp110 = fmul float %tmp109, %tmp106
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%tmp111 = fsub float -0.000000e+00, %tmp105
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%tmp112 = fmul float %tmp111, %tmp106
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%tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110)
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%tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0
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ret void
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}
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; We just want ot make sure the program doesn't crash
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; CHECK-LABEL: {{^}}loop:
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define amdgpu_ps void @loop(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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main_body:
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%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
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%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0)
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%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 4)
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%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 8)
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%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 12)
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%tmp25 = fptosi float %tmp24 to i32
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%tmp26 = bitcast i32 %tmp25 to float
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%tmp27 = bitcast float %tmp26 to i32
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br label %LOOP
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LOOP: ; preds = %ENDIF, %main_body
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%temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ]
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%temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ]
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%temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ]
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%temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ]
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%tmp28 = bitcast float %temp8.0 to i32
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%tmp29 = icmp sge i32 %tmp28, %tmp27
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%tmp30 = sext i1 %tmp29 to i32
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%tmp31 = bitcast i32 %tmp30 to float
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%tmp32 = bitcast float %tmp31 to i32
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%tmp33 = icmp ne i32 %tmp32, 0
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br i1 %tmp33, label %IF, label %ENDIF
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IF: ; preds = %LOOP
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0
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ret void
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ENDIF: ; preds = %LOOP
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%tmp34 = bitcast float %temp8.0 to i32
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%tmp35 = add i32 %tmp34, 1
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%tmp36 = bitcast i32 %tmp35 to float
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br label %LOOP
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}
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; This checks for a bug in the FixSGPRCopies pass where VReg96
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; registers were being identified as an SGPR regclass which was causing
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; an assertion failure.
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; CHECK-LABEL: {{^}}sample_v3:
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; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11
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; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13
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; CHECK: s_branch
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; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
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; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
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; CHECK: BB{{[0-9]+_[0-9]+}}:
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; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}}
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; CHECK: exp
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; CHECK: s_endpgm
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define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
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entry:
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%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
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%tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
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%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 16)
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%tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
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%tmp24 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp23, !tbaa !0
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%tmp25 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0
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%tmp26 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp25, !tbaa !0
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%tmp27 = fcmp oeq float %tmp22, 0.000000e+00
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%tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32>
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br i1 %tmp27, label %if, label %else
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if: ; preds = %entry
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%tmp1 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 0x36D6000000000000, float 0x36DA000000000000>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
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%val.if.0 = extractelement <4 x float> %tmp1, i32 0
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%val.if.1 = extractelement <4 x float> %tmp1, i32 1
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%val.if.2 = extractelement <4 x float> %tmp1, i32 2
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br label %endif
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else: ; preds = %entry
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%tmp2 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 0x36C4000000000000, float 0x36CC000000000000>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
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%val.else.0 = extractelement <4 x float> %tmp2, i32 0
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%val.else.1 = extractelement <4 x float> %tmp2, i32 1
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%val.else.2 = extractelement <4 x float> %tmp2, i32 2
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br label %endif
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endif: ; preds = %else, %if
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%val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ]
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%val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ]
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%val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ]
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0
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ret void
|
|
}
|
|
|
|
; CHECK-LABEL: {{^}}copy1:
|
|
; CHECK: buffer_load_dword
|
|
; CHECK: v_add
|
|
; CHECK: s_endpgm
|
|
define amdgpu_kernel void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) {
|
|
entry:
|
|
%tmp = load float, float addrspace(1)* %in0
|
|
%tmp1 = fcmp oeq float %tmp, 0.000000e+00
|
|
br i1 %tmp1, label %if0, label %endif
|
|
|
|
if0: ; preds = %entry
|
|
%tmp2 = bitcast float %tmp to i32
|
|
%tmp3 = fcmp olt float %tmp, 0.000000e+00
|
|
br i1 %tmp3, label %if1, label %endif
|
|
|
|
if1: ; preds = %if0
|
|
%tmp4 = add i32 %tmp2, 1
|
|
br label %endif
|
|
|
|
endif: ; preds = %if1, %if0, %entry
|
|
%tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ]
|
|
%tmp6 = bitcast i32 %tmp5 to float
|
|
store float %tmp6, float addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; This test is just checking that we don't crash / assertion fail.
|
|
; CHECK-LABEL: {{^}}copy2:
|
|
; CHECK: s_endpgm
|
|
define amdgpu_ps void @copy2([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
|
|
entry:
|
|
br label %LOOP68
|
|
|
|
LOOP68: ; preds = %ENDIF69, %entry
|
|
%temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
|
|
%t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
|
|
%g = icmp eq i32 0, %t
|
|
%l = bitcast float %temp4.7 to i32
|
|
br i1 %g, label %IF70, label %ENDIF69
|
|
|
|
IF70: ; preds = %LOOP68
|
|
%q = icmp ne i32 %l, 13
|
|
%temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
|
|
ret void
|
|
|
|
ENDIF69: ; preds = %LOOP68
|
|
%u = add i32 %l, %t
|
|
%v = bitcast i32 %u to float
|
|
%x = add i32 %t, -1
|
|
br label %LOOP68
|
|
}
|
|
|
|
; This test checks that image_sample resource descriptors aren't loaded into
|
|
; vgprs. The verifier will fail if this happens.
|
|
; CHECK-LABEL:{{^}}sample_rsrc
|
|
|
|
; CHECK: s_cmp_eq_u32
|
|
; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]]
|
|
|
|
; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
|
|
|
|
; [[END]]:
|
|
; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}}
|
|
; CHECK: s_endpgm
|
|
define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* byval %arg, [17 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <4 x i32>] addrspace(4)* byval %arg2, [32 x <8 x i32>] addrspace(4)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
|
|
bb:
|
|
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i32 0, i32 0
|
|
%tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !3
|
|
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp22, i32 16)
|
|
%tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(4)* %arg3, i32 0, i32 0
|
|
%tmp26 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp25, !tbaa !3
|
|
%tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(4)* %arg2, i32 0, i32 0
|
|
%tmp28 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp27, !tbaa !3
|
|
%i.i = extractelement <2 x i32> %arg7, i32 0
|
|
%j.i = extractelement <2 x i32> %arg7, i32 1
|
|
%i.f.i = bitcast i32 %i.i to float
|
|
%j.f.i = bitcast i32 %j.i to float
|
|
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0
|
|
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0
|
|
%i.i1 = extractelement <2 x i32> %arg7, i32 0
|
|
%j.i2 = extractelement <2 x i32> %arg7, i32 1
|
|
%i.f.i3 = bitcast i32 %i.i1 to float
|
|
%j.f.i4 = bitcast i32 %j.i2 to float
|
|
%p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0
|
|
%p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0
|
|
%tmp31 = bitcast float %tmp23 to i32
|
|
%tmp36 = icmp ne i32 %tmp31, 0
|
|
br i1 %tmp36, label %bb38, label %bb80
|
|
|
|
bb38: ; preds = %bb
|
|
%tmp52 = bitcast float %p2.i to i32
|
|
%tmp53 = bitcast float %p2.i6 to i32
|
|
%tmp54 = insertelement <2 x i32> undef, i32 %tmp52, i32 0
|
|
%tmp55 = insertelement <2 x i32> %tmp54, i32 %tmp53, i32 1
|
|
%tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32>
|
|
%a.bc.i = bitcast <2 x i32> %tmp55 to <2 x float>
|
|
%tmp2 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %a.bc.i, <8 x i32> %tmp56, <4 x i32> %tmp28, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
|
|
br label %bb71
|
|
|
|
bb80: ; preds = %bb
|
|
%tmp81 = bitcast float %p2.i to i32
|
|
%tmp82 = bitcast float %p2.i6 to i32
|
|
%tmp82.2 = add i32 %tmp82, 1
|
|
%tmp83 = insertelement <2 x i32> undef, i32 %tmp81, i32 0
|
|
%tmp84 = insertelement <2 x i32> %tmp83, i32 %tmp82.2, i32 1
|
|
%tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32>
|
|
%a.bc.i1 = bitcast <2 x i32> %tmp84 to <2 x float>
|
|
%tmp3 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %a.bc.i1, <8 x i32> %tmp85, <4 x i32> %tmp28, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
|
|
br label %bb71
|
|
|
|
bb71: ; preds = %bb80, %bb38
|
|
%tmp72 = phi <4 x float> [ %tmp2, %bb38 ], [ %tmp3, %bb80 ]
|
|
%tmp88 = extractelement <4 x float> %tmp72, i32 0
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0
|
|
ret void
|
|
}
|
|
|
|
; Check the resource descriptor is stored in an sgpr.
|
|
; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
|
|
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
|
define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(4)* byval %arg) #0 {
|
|
bb:
|
|
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
|
|
%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i32 0, i32 %tid
|
|
%tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0
|
|
%tmp = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 7.500000e-01, float 2.500000e-01>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
|
|
%tmp10 = extractelement <4 x float> %tmp, i32 0
|
|
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10)
|
|
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
|
|
ret void
|
|
}
|
|
|
|
; Check the sampler is stored in an sgpr.
|
|
; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
|
|
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
|
define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(4)* byval %arg) #0 {
|
|
bb:
|
|
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
|
|
%tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i32 0, i32 %tid
|
|
%tmp8 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp7, align 16, !tbaa !0
|
|
%tmp = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 7.500000e-01, float 2.500000e-01>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
|
|
%tmp10 = extractelement <4 x float> %tmp, i32 0
|
|
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
|
|
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
|
|
ret void
|
|
}
|
|
|
|
declare float @llvm.fabs.f32(float) #1
|
|
declare float @llvm.amdgcn.rsq.f32(float) #1
|
|
declare float @llvm.exp2.f32(float) #1
|
|
declare float @llvm.pow.f32(float, float) #1
|
|
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
|
|
declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
|
|
declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
|
|
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
|
declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
|
|
declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
|
|
declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
|
|
declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|
|
attributes #2 = { nounwind readonly }
|
|
|
|
!0 = !{!1, !1, i64 0, i32 1}
|
|
!1 = !{!"const", !2}
|
|
!2 = !{!"tbaa root"}
|
|
!3 = !{!1, !1, i64 0}
|