llvm-project/llvm/test/MC/Disassembler
Wouter van Oortmerssen a90d24da1c Revert "[WebAssembly] Added default stack-only instruction mode for MC."
This reverts commit d3c9af4179eae7793d1487d652e2d4e23844555f.
(SVN revision 338164)

llvm-svn: 338176
2018-07-27 23:19:51 +00:00
..
AArch64 [AArch64] Armv8.2-A: add the crypto extensions 2018-07-26 07:13:59 +00:00
AMDGPU AMDGPU: Fix v_dot{4, 8}* instruction encoding 2018-05-15 19:32:47 +00:00
ARC [ARC] Add LImm support for J/JL 2018-04-13 15:10:34 +00:00
ARM [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction 2018-07-06 08:03:12 +00:00
Hexagon NFC - Various typo fixes in tests 2018-07-04 13:28:39 +00:00
Lanai
Mips [mips] Correct the predicates of arithmetic and logic instructions. 2018-05-30 11:33:35 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly Revert "[WebAssembly] Added default stack-only instruction mode for MC." 2018-07-27 23:19:51 +00:00
X86 [X86][Disassembler] Fix LOCK prefix disassembler support 2018-07-05 23:32:42 +00:00
XCore