forked from OSchip/llvm-project
113 lines
3.1 KiB
LLVM
113 lines
3.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i16 0, align 2
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
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entry:
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%cmp = icmp uge i16 %a, %b
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%conv3 = zext i1 %cmp to i64
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ret i64 %conv3
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; CHECK-LABEL: test_llgeus:
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
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; CHECK: xori r3, [[REG2]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
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entry:
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%cmp = icmp uge i16 %a, %b
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%conv3 = sext i1 %cmp to i64
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ret i64 %conv3
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; CHECK-LABEL: @test_llgeus_sext
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeus_z(i16 zeroext %a) {
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entry:
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%cmp = icmp uge i16 %a, 0
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llgeus_z
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; CHECK: li r3, 1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @test_llgeus_sext_z(i16 zeroext %a) {
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entry:
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%cmp = icmp uge i16 %a, 0
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%conv1 = sext i1 %cmp to i64
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ret i64 %conv1
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; CHECK-LABEL: @test_llgeus_sext_z
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; CHECK: li r3, -1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
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entry:
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%cmp = icmp uge i16 %a, %b
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%conv3 = zext i1 %cmp to i16
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store i16 %conv3, i16* @glob
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ret void
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; CHECK_LABEL: test_llgeus_store:
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
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; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
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entry:
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%cmp = icmp uge i16 %a, %b
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%conv3 = sext i1 %cmp to i16
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store i16 %conv3, i16* @glob
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ret void
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; CHECK-LABEL: @test_llgeus_sext_store
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; CHECK: sub [[REG1:r[0-9]+]], r3, r4
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK: sth [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeus_z_store(i16 zeroext %a) {
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entry:
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%cmp = icmp uge i16 %a, 0
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%conv1 = zext i1 %cmp to i16
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store i16 %conv1, i16* @glob
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ret void
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; CHECK-LABEL: @test_llgeus_z_store
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; CHECK: li [[REG1:r[0-9]+]], 1
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; CHECK: sth [[REG1]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_llgeus_sext_z_store(i16 zeroext %a) {
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entry:
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%cmp = icmp uge i16 %a, 0
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%conv1 = sext i1 %cmp to i16
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store i16 %conv1, i16* @glob
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ret void
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; CHECK-LABEL: @test_llgeus_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: sth [[REG1]]
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; CHECK: blr
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}
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