forked from OSchip/llvm-project
115 lines
4.2 KiB
LLVM
115 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
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define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
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; CHECK-LABEL: load_store_v1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e8,mf8,ta,mu
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; CHECK-NEXT: vle1.v v0, (a0)
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; CHECK-NEXT: vmv.v.i v25, 0
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; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmv.v.i v26, 0
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; CHECK-NEXT: vsetivli zero, 1, e8,mf2,tu,mu
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; CHECK-NEXT: vslideup.vi v26, v25, 0
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmsne.vi v25, v26, 0
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; CHECK-NEXT: vse1.v v25, (a1)
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; CHECK-NEXT: ret
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%a = load <1 x i1>, <1 x i1>* %x
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store <1 x i1> %a, <1 x i1>* %y
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ret void
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}
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define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
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; CHECK-LABEL: load_store_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e8,mf8,ta,mu
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; CHECK-NEXT: vle1.v v0, (a0)
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; CHECK-NEXT: vmv.v.i v25, 0
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; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmv.v.i v26, 0
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; CHECK-NEXT: vsetivli zero, 2, e8,mf2,tu,mu
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; CHECK-NEXT: vslideup.vi v26, v25, 0
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmsne.vi v25, v26, 0
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; CHECK-NEXT: vse1.v v25, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x i1>, <2 x i1>* %x
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store <2 x i1> %a, <2 x i1>* %y
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ret void
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}
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define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
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; CHECK-LABEL: load_store_v4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e8,mf4,ta,mu
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; CHECK-NEXT: vle1.v v0, (a0)
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; CHECK-NEXT: vmv.v.i v25, 0
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; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmv.v.i v26, 0
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; CHECK-NEXT: vsetivli zero, 4, e8,mf2,tu,mu
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; CHECK-NEXT: vslideup.vi v26, v25, 0
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vmsne.vi v25, v26, 0
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; CHECK-NEXT: vse1.v v25, (a1)
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; CHECK-NEXT: ret
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%a = load <4 x i1>, <4 x i1>* %x
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store <4 x i1> %a, <4 x i1>* %y
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ret void
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}
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define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
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; CHECK-LABEL: load_store_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8,mf2,ta,mu
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; CHECK-NEXT: vle1.v v25, (a0)
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; CHECK-NEXT: vse1.v v25, (a1)
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; CHECK-NEXT: ret
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%a = load <8 x i1>, <8 x i1>* %x
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store <8 x i1> %a, <8 x i1>* %y
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ret void
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}
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define void @load_store_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
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; CHECK-LABEL: load_store_v16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8,m1,ta,mu
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; CHECK-NEXT: vle1.v v25, (a0)
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; CHECK-NEXT: vse1.v v25, (a1)
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; CHECK-NEXT: ret
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%a = load <16 x i1>, <16 x i1>* %x
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store <16 x i1> %a, <16 x i1>* %y
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ret void
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}
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define void @load_store_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
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; LMULMAX2-LABEL: load_store_v32i1:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: addi a2, zero, 32
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; LMULMAX2-NEXT: vsetvli zero, a2, e8,m2,ta,mu
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; LMULMAX2-NEXT: vle1.v v25, (a0)
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; LMULMAX2-NEXT: vse1.v v25, (a1)
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; LMULMAX2-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: load_store_v32i1:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: lw a0, 0(a0)
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; LMULMAX1-RV32-NEXT: sw a0, 0(a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: load_store_v32i1:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: lw a0, 0(a0)
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; LMULMAX1-RV64-NEXT: sw a0, 0(a1)
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; LMULMAX1-RV64-NEXT: ret
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%a = load <32 x i1>, <32 x i1>* %x
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store <32 x i1> %a, <32 x i1>* %y
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ret void
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}
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