forked from OSchip/llvm-project
255 lines
9.6 KiB
LLVM
255 lines
9.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
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define void @abs_v16i8(<16 x i8>* %x, <16 x i8>* %y) {
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; CHECK-LABEL: abs_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8,m1,ta,mu
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; CHECK-NEXT: vle8.v v25, (a0)
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; CHECK-NEXT: vrsub.vi v26, v25, 0
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; CHECK-NEXT: vmax.vv v25, v25, v26
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; CHECK-NEXT: vse8.v v25, (a0)
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; CHECK-NEXT: ret
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%a = load <16 x i8>, <16 x i8>* %x
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%b = load <16 x i8>, <16 x i8>* %y
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%c = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false)
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store <16 x i8> %c, <16 x i8>* %x
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ret void
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}
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declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
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define void @abs_v8i16(<8 x i16>* %x, <8 x i16>* %y) {
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; CHECK-LABEL: abs_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu
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; CHECK-NEXT: vle16.v v25, (a0)
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; CHECK-NEXT: vrsub.vi v26, v25, 0
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; CHECK-NEXT: vmax.vv v25, v25, v26
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; CHECK-NEXT: vse16.v v25, (a0)
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; CHECK-NEXT: ret
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%a = load <8 x i16>, <8 x i16>* %x
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%b = load <8 x i16>, <8 x i16>* %y
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%c = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false)
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store <8 x i16> %c, <8 x i16>* %x
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ret void
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}
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declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
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define void @abs_v4i32(<4 x i32>* %x, <4 x i32>* %y) {
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; CHECK-LABEL: abs_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32,m1,ta,mu
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; CHECK-NEXT: vle32.v v25, (a0)
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; CHECK-NEXT: vrsub.vi v26, v25, 0
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; CHECK-NEXT: vmax.vv v25, v25, v26
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; CHECK-NEXT: vse32.v v25, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x i32>, <4 x i32>* %x
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%b = load <4 x i32>, <4 x i32>* %y
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%c = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)
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store <4 x i32> %c, <4 x i32>* %x
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ret void
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}
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declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
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define void @abs_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
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; CHECK-LABEL: abs_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64,m1,ta,mu
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; CHECK-NEXT: vle64.v v25, (a0)
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; CHECK-NEXT: vrsub.vi v26, v25, 0
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; CHECK-NEXT: vmax.vv v25, v25, v26
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; CHECK-NEXT: vse64.v v25, (a0)
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; CHECK-NEXT: ret
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%a = load <2 x i64>, <2 x i64>* %x
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%b = load <2 x i64>, <2 x i64>* %y
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%c = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 false)
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store <2 x i64> %c, <2 x i64>* %x
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ret void
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}
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declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
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define void @abs_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
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; LMULMAX2-LABEL: abs_v32i8:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: addi a1, zero, 32
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; LMULMAX2-NEXT: vsetvli zero, a1, e8,m2,ta,mu
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; LMULMAX2-NEXT: vle8.v v26, (a0)
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; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
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; LMULMAX2-NEXT: vmax.vv v26, v26, v28
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; LMULMAX2-NEXT: vse8.v v26, (a0)
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; LMULMAX2-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: abs_v32i8:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8,m1,ta,mu
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; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vle8.v v25, (a1)
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; LMULMAX1-RV32-NEXT: vle8.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV32-NEXT: vse8.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vse8.v v25, (a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: abs_v32i8:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8,m1,ta,mu
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; LMULMAX1-RV64-NEXT: addi a1, a0, 16
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; LMULMAX1-RV64-NEXT: vle8.v v25, (a1)
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; LMULMAX1-RV64-NEXT: vle8.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV64-NEXT: vse8.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vse8.v v25, (a1)
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; LMULMAX1-RV64-NEXT: ret
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%a = load <32 x i8>, <32 x i8>* %x
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%b = load <32 x i8>, <32 x i8>* %y
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%c = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false)
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store <32 x i8> %c, <32 x i8>* %x
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ret void
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}
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declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)
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define void @abs_v16i16(<16 x i16>* %x, <16 x i16>* %y) {
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; LMULMAX2-LABEL: abs_v16i16:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: vsetivli zero, 16, e16,m2,ta,mu
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; LMULMAX2-NEXT: vle16.v v26, (a0)
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; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
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; LMULMAX2-NEXT: vmax.vv v26, v26, v28
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; LMULMAX2-NEXT: vse16.v v26, (a0)
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; LMULMAX2-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: abs_v16i16:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16,m1,ta,mu
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; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vle16.v v25, (a1)
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; LMULMAX1-RV32-NEXT: vle16.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV32-NEXT: vse16.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vse16.v v25, (a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: abs_v16i16:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16,m1,ta,mu
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; LMULMAX1-RV64-NEXT: addi a1, a0, 16
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; LMULMAX1-RV64-NEXT: vle16.v v25, (a1)
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; LMULMAX1-RV64-NEXT: vle16.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV64-NEXT: vse16.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vse16.v v25, (a1)
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; LMULMAX1-RV64-NEXT: ret
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%a = load <16 x i16>, <16 x i16>* %x
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%b = load <16 x i16>, <16 x i16>* %y
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%c = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false)
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store <16 x i16> %c, <16 x i16>* %x
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ret void
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}
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declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)
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define void @abs_v8i32(<8 x i32>* %x, <8 x i32>* %y) {
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; LMULMAX2-LABEL: abs_v8i32:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: vsetivli zero, 8, e32,m2,ta,mu
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; LMULMAX2-NEXT: vle32.v v26, (a0)
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; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
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; LMULMAX2-NEXT: vmax.vv v26, v26, v28
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; LMULMAX2-NEXT: vse32.v v26, (a0)
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; LMULMAX2-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: abs_v8i32:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu
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; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vle32.v v25, (a1)
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; LMULMAX1-RV32-NEXT: vle32.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV32-NEXT: vse32.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vse32.v v25, (a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: abs_v8i32:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32,m1,ta,mu
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; LMULMAX1-RV64-NEXT: addi a1, a0, 16
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; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
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; LMULMAX1-RV64-NEXT: vle32.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV64-NEXT: vse32.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vse32.v v25, (a1)
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; LMULMAX1-RV64-NEXT: ret
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%a = load <8 x i32>, <8 x i32>* %x
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%b = load <8 x i32>, <8 x i32>* %y
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%c = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false)
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store <8 x i32> %c, <8 x i32>* %x
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ret void
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}
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declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
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define void @abs_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
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; LMULMAX2-LABEL: abs_v4i64:
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; LMULMAX2: # %bb.0:
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; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu
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; LMULMAX2-NEXT: vle64.v v26, (a0)
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; LMULMAX2-NEXT: vrsub.vi v28, v26, 0
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; LMULMAX2-NEXT: vmax.vv v26, v26, v28
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; LMULMAX2-NEXT: vse64.v v26, (a0)
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; LMULMAX2-NEXT: ret
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;
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; LMULMAX1-RV32-LABEL: abs_v4i64:
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; LMULMAX1-RV32: # %bb.0:
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; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu
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; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vle64.v v25, (a1)
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; LMULMAX1-RV32-NEXT: vle64.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV32-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV32-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV32-NEXT: vse64.v v26, (a0)
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; LMULMAX1-RV32-NEXT: vse64.v v25, (a1)
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; LMULMAX1-RV32-NEXT: ret
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;
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; LMULMAX1-RV64-LABEL: abs_v4i64:
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; LMULMAX1-RV64: # %bb.0:
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; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu
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; LMULMAX1-RV64-NEXT: addi a1, a0, 16
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; LMULMAX1-RV64-NEXT: vle64.v v25, (a1)
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; LMULMAX1-RV64-NEXT: vle64.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v25, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v25, v25, v27
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; LMULMAX1-RV64-NEXT: vrsub.vi v27, v26, 0
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; LMULMAX1-RV64-NEXT: vmax.vv v26, v26, v27
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; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
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; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
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; LMULMAX1-RV64-NEXT: ret
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%a = load <4 x i64>, <4 x i64>* %x
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%b = load <4 x i64>, <4 x i64>* %y
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%c = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false)
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store <4 x i64> %c, <4 x i64>* %x
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ret void
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}
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declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
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