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llvm-project/llvm/test/CodeGen/RISCV/rvv
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Craig Topper c653711fd3 [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 
All that really matters is that the VLMAX of the preceding
instructions is the same as the VLMAX required by the mask
operation.

Also update the vmsge(u) handling to use the SEW/LMUL we use for
other mask register operations. We were matching it to the compare
before. Some cases will be improve if we fix masked compares to
use tail agnostic policy. I think they ignore the tail policy
anyway.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D103299
 		2021-06-04 09:17:46 -07:00
..
abs-sdnode.ll [RISCV] Optimize fixed vector ABS. Fix crash on scalable vector ABS for SEW=64 with RV32. 2021-03-09 08:51:03 -08:00
access-fixed-objects-by-rvv.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
addi-scalable-offset.mir [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
allocate-lmul-2-4-8.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
calling-conv-fastcc.ll [RISCV] Support vector types in combination with fastcc 2021-06-01 10:31:18 +01:00
calling-conv.ll [RISCV] Scale scalably-typed split argument offsets by VSCALE 2021-05-31 10:43:13 +01:00
combine-store-fp.ll [DAGCombine][RISCV] Don't try to trunc-store combined vector stores 2021-05-27 14:16:32 +01:00
constant-folding.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
emergency-slot.mir [RISCV] Further fixes for RVV stack offset computation 2021-04-21 10:51:07 +01:00
extload-truncstore.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
extract-subvector.ll [RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types 2021-03-01 11:51:05 +00:00
extractelt-fp-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
extractelt-fp-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
extractelt-i1.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
extractelt-int-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
extractelt-int-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-abs.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-bitcast.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-bitreverse.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-bswap.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-calling-conv-fastcc.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-calling-conv.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-ctlz.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-ctpop.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-cttz.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-emergency-slot.mir [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-extload-truncstore.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
fixed-vectors-extract-i1.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-extract-subvector.ll [RISCV] Remove earlyclobber from compares with LMUL<=1. 2021-06-01 09:08:11 -07:00
fixed-vectors-extract.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-fp-bitcast.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-fp-buildvec.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-fp-conv.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-fp-setcc.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
fixed-vectors-fp-shuffles.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-fp-splat.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-fp-vrgather.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-fp.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-fp2i.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
fixed-vectors-i2fp.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-insert-i1.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-insert-subvector.ll [RISCV] Remove earlyclobber from compares with LMUL<=1. 2021-06-01 09:08:11 -07:00
fixed-vectors-insert.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-int-buildvec.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-int-exttrunc.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
fixed-vectors-int-setcc.ll [RISCV] Remove earlyclobber from compares with LMUL<=1. 2021-06-01 09:08:11 -07:00
fixed-vectors-int-shuffles.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-int-splat.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-int-vrgather.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-int.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-mask-buildvec.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-mask-load-store.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-mask-logic.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-mask-splat.ll [RISCV] Remove earlyclobber from compares with LMUL<=1. 2021-06-01 09:08:11 -07:00
fixed-vectors-masked-gather.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
fixed-vectors-masked-load-fp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-masked-load-int.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-masked-scatter.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
fixed-vectors-masked-store-fp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-masked-store-int.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-reduction-fp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-reduction-int.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-select-fp.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-select-int.ll [RISCV] Remove earlyclobber from compares with LMUL<=1. 2021-06-01 09:08:11 -07:00
fixed-vectors-stepvector-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-stepvector-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-unaligned.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
fixed-vectors-vadd-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vand-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vdiv-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vdivu-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vfmax.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vfmin.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vmul-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vnsra-vnsrl.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
fixed-vectors-vor-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vreductions-mask.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vrem-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vremu-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vrsub-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vselect.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
fixed-vectors-vshl-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vsra-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vsrl-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vsub-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
fixed-vectors-vxor-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
frameindex-addr.ll [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
get-vlen-debugloc.mir [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
inline-asm.ll [RISCV] Support inline asm for vector instructions. 2021-03-15 11:02:18 +08:00
insert-subvector.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
insertelt-fp-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
insertelt-fp-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
insertelt-i1.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
insertelt-int-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
insertelt-int-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
interleave-crash.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
legalize-scalable-vectortype.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
load-add-store-8.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-add-store-16.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-add-store-32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-add-store-64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-mask.ll [RISCV] Load/store vector mask types. 2021-02-03 13:44:15 +08:00
localvar.ll [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
mask-exts-truncs-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
mask-exts-truncs-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
mask-reg-alloc.mir [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
masked-load-fp.ll [RISCV] Look through copies when trying to find an implicit def in addVSetVL. 2021-03-16 07:59:09 -07:00
masked-load-int.ll [RISCV] Look through copies when trying to find an implicit def in addVSetVL. 2021-03-16 07:59:09 -07:00
masked-store-fp.ll [RISCV] Add support for scalable vector masked load/store. 2021-03-12 10:32:33 -08:00
masked-store-int.ll [DAGCombiner] Use isConstantSplatVectorAllZeros/Ones instead of isBuildVectorAllZeros/Ones in visitMSTORE and visitMLOAD. 2021-03-12 12:14:56 -08:00
memory-args.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
mgather-sdnode.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
mscatter-sdnode.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
named-vector-shuffle-reverse.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
regalloc-fast-crash.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
rv32-spill-vector-csr.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
rv32-spill-vector.ll change rvv frame layout 2021-03-13 16:05:55 +08:00
rv32-spill-zvlsseg.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
rv32-vsetvli-intrinsics.ll [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
rv64-spill-vector-csr.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
rv64-spill-vector.ll change rvv frame layout 2021-03-13 16:05:55 +08:00
rv64-spill-zvlsseg.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
rv64-vsetvli-intrinsics.ll [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
rvv-framelayout.ll [RISCV] Optimize getVLENFactoredAmount function. 2021-05-24 10:04:37 -07:00
rvv-out-arguments.ll [RISCV] Precommit a test case to show overwriting vector frame objects. 2021-06-03 23:25:45 +08:00
rvv-vscale.i32.ll [RISCV] Custom lower ISD::VSCALE. 2021-01-13 17:14:49 -08:00
rvv-vscale.i64.ll [RISCV] Custom lower ISD::VSCALE. 2021-01-13 17:14:49 -08:00
saddo-sdnode.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
select-fp.ll [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion 2021-05-10 08:22:35 +01:00
select-int.ll [RISCV] Remove earlyclobber from compares with LMUL<=1. 2021-06-01 09:08:11 -07:00
select-sra.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
setcc-fp-rv32.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
setcc-fp-rv64.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
setcc-integer-rv32.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
setcc-integer-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
stepvector.ll [RISCV][NFC] Simplify test run lines 2021-05-13 12:41:00 +01:00
tail-agnostic-impdef-copy.mir [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
unsupported-calling-conv.ll [RISCV] Allow passing fixed-length vectors via the stack 2021-05-27 14:14:07 +01:00
vaadd-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vaadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vaaddu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vaaddu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vadc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vadc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vadd-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vadd-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vadd-sdnode-rv64.ll [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR 2021-04-07 10:03:33 -07:00
vadd-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoadd-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoand-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoand-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamomax-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamomax-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamomaxu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamomaxu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamomin-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamomin-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamominu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamominu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoswap-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoswap-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoxor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vamoxor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vand-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vand-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vand-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vand-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vand-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vasub-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vasub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vasubu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vasubu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vcompress-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vcompress-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vdiv-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vdiv-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vdiv-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vdiv-sdnode-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vdiv-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vdivu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vdivu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vdivu-sdnode-rv32.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
vdivu-sdnode-rv64.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
vdivu-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vexts-sdnode-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vexts-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfabs-sdnode.ll [RISCV] Add patterns for scalable-vector fabs & fcopysign 2021-02-16 10:21:09 +00:00
vfadd-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfadd-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfclass-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfclass-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcopysign-sdnode.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vfcvt-f-x-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-f-x-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-f-xu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-f-xu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-rtz-x-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-rtz-x-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-rtz-xu-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-rtz-xu-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-x-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-x-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-xu-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfcvt-xu-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfdiv-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfdiv-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfdiv-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfirst-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfirst-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmacc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmacc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmadd-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmadd-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmax-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmax-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmax-sdnode.ll [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) 2021-04-23 12:22:15 +01:00
vfmerge-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmerge-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmin-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmin-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmin-sdnode.ll [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) 2021-04-23 12:22:15 +01:00
vfmsac-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmsac-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmsub-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmsub-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmul-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmul-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmul-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfmv.f.s.ll [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
vfmv.s.f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmv.s.f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmv.v.f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfmv.v.f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-f-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-f-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-f-x-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-f-x-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-f-xu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-f-xu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-rod-f-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-rod-f-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-rtz-x-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-rtz-x-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-rtz-xu-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-rtz-xu-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-x-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-x-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-xu-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfncvt-xu-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfneg-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfnmacc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmacc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmadd-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmadd-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfnmsac-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmsac-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmsub-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfnmsub-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfpext-sdnode.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vfptoi-sdnode.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vfptrunc-sdnode.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vfrdiv-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrdiv-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrec7-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrec7-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredmax-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredmax-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredmin-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredmin-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredosum-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredosum-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredsum-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfredsum-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrsqrt7-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrsqrt7-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrsub-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfrsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsgnj-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsgnj-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsgnjn-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsgnjn-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsgnjx-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsgnjx-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfslide1down-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfslide1down-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfslide1up-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfslide1up-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsqrt-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsqrt-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsqrt-sdnode.ll [RISCV] Add patterns for scalable-vector fsqrt 2021-02-05 09:39:19 +00:00
vfsub-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfsub-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfwadd-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwadd.w-rv32.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vfwadd.w-rv64.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vfwcvt-f-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-f-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-f-x-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-f-x-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-f-xu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-f-xu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-rtz-x-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-rtz-x-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-rtz-xu-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-rtz-xu-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-x-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-x-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-xu-f-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwcvt-xu-f-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwmacc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwmacc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwmsac-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwmsac-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwmul-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwmul-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwnmacc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwnmacc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwnmsac-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwnmsac-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwredosum-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwredosum-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwredsum-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwredsum-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwsub-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vfwsub.w-rv32.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vfwsub.w-rv64.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vid-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vid-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
viota-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
viota-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vitofp-sdnode.ll [RISCV] Support vector conversions between fp and i1 2021-05-31 09:55:39 +01:00
vle-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vle-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vle1-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vle1-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vleff-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vleff-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vloxei-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vloxei-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vloxseg-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vloxseg-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlse-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlse-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlseg-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vlseg-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vlsegff-rv32-dead.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlsegff-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlsegff-rv64-dead.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlsegff-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vlsseg-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vlsseg-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vluxei-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vluxei-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vluxseg-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vluxseg-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmacc-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmacc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmadc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmadc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmadc.carry.in-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmadc.carry.in-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmadd-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmand-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmand-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmandnot-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmandnot-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmarith-sdnode.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmax-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmax-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmax-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmax-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmaxu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmaxu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmaxu-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmaxu-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmclr-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmclr-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmerge-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmerge-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmfeq-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfeq-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfge-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfge-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfgt-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfgt-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfle-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfle-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmflt-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmflt-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfne-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmfne-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmin-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmin-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmin-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmin-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vminu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vminu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vminu-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vminu-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmnand-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmnand-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmnor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmnor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmornot-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmornot-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsbc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsbc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsbc.borrow.in-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsbc.borrow.in-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsbf-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsbf-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmseq-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmseq-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmset-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmset-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsge-rv32.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
vmsge-rv64.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
vmsgeu-rv32.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
vmsgeu-rv64.ll [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. 2021-06-04 09:17:46 -07:00
vmsgt-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsgt-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsgtu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsgtu-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsif-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsif-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsle-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsle-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsleu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsleu-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmslt-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmslt-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsltu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsltu-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsne-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsne-rv64.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmsof-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmsof-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmul-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmul-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmul-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmul-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmul-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmulh-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmulh-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmulh-sdnode-rv32.ll [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR 2021-04-07 10:03:33 -07:00
vmulhsu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmulhsu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmulhu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vmulhu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.s.x-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.s.x-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.v.v-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.v.v-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.v.x-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.v.x-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.x.s-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmv.x.s-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmxnor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmxnor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmxor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vmxor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vnclip-rv32.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnclip-rv64.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnclipu-rv32.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnclipu-rv64.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnmsac-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vnmsac-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vnmsub-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vnmsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vnsra-rv32.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnsra-rv64.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnsrl-rv32.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vnsrl-rv64.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vor-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vor-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vor-sdnode-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vor-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vpopc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vpopc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredand-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredand-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredmax-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredmax-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredmaxu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredmaxu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredmin-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredmin-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredminu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredminu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredsum-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredsum-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vreductions-fp-sdnode.ll [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
vreductions-int-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vreductions-int-rv64.ll [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
vreductions-mask.ll [RISCV] Support OR/XOR/AND reductions on vector masks 2021-04-08 09:46:38 +01:00
vredxor-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vredxor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrem-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vrem-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrem-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vrem-sdnode-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vrem-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vremu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vremu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vremu-sdnode-rv32.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
vremu-sdnode-rv64.ll [SelectionDAG] Extend FoldConstantVectorArithmetic to SPLAT_VECTOR 2021-06-04 09:53:15 +01:00
vremu-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrgather-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrgather-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrgatherei16-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrgatherei16-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrsub-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vrsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vrsub-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vrsub-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vrsub-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsadd-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vsadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsaddu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vsaddu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsbc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsbc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vse-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vse-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vse1-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vse1-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vselect-fp-rv32.ll [CodeGen] Fix a scalable-vector crash in VSELECT legalization 2021-06-03 10:24:55 +01:00
vselect-fp-rv64.ll [CodeGen] Fix a scalable-vector crash in VSELECT legalization 2021-06-03 10:24:55 +01:00
vselect-int-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vselect-int-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vselect-mask.ll [SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs 2021-05-27 10:08:57 +01:00
vsetvl-ext.ll [RISCV] Teach computeKnownBits that vsetvli returns number less than 2^31. 2021-04-29 08:07:59 -07:00
vsetvli-insert-crossbb.ll [RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli. 2021-05-27 15:34:08 -07:00
vsetvli-insert-crossbb.mir [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vsetvli-insert.mir [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vsext-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsext-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vshl-sdnode-rv32.ll [RISCV] Optimize SEW=64 shifts by splat on RV32. 2021-05-26 10:23:32 -07:00
vshl-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vshl-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslide1down-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslide1down-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslide1up-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslide1up-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslidedown-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslidedown-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslideup-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vslideup-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsll-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsll-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsmul-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vsmul-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsoxei-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsoxei-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsoxseg-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsoxseg-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsplats-fp.ll [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR. 2021-01-26 01:00:50 -08:00
vsplats-i1.ll [RISCV] Lower splats of non-constant i1s as SETCCs 2021-05-04 09:14:05 +01:00
vsplats-i64.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vsra-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsra-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsra-sdnode-rv32.ll [RISCV] Optimize SEW=64 shifts by splat on RV32. 2021-05-26 10:23:32 -07:00
vsra-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsra-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsrl-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsrl-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsrl-sdnode-rv32.ll [RISCV] Optimize SEW=64 shifts by splat on RV32. 2021-05-26 10:23:32 -07:00
vsrl-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsrl-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsse-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsse-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsseg-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsseg-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssra-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssra-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssrl-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssrl-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssseg-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssseg-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssub-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vssub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vssubu-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vssubu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsub-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsub-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vsub-sdnode-rv64.ll [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR 2021-04-07 10:03:33 -07:00
vsub-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsuxei-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsuxei-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsuxseg-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vsuxseg-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vtruncs-sdnode-rv32.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vtruncs-sdnode-rv64.ll [RISCV] Remove earlyclobber from vnsrl/vnsra/vnclip(u) when the source and dest are a single vector register. 2021-06-01 09:17:52 -07:00
vwadd-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwadd-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwadd.w-rv32.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwadd.w-rv64.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwaddu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwaddu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwaddu.w-rv32.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwaddu.w-rv64.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwmacc-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmacc-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmaccsu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmaccsu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmaccu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmaccu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmaccus-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmaccus-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmul-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmul-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmulsu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmulsu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmulu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwmulu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwredsum-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwredsum-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwredsumu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwredsumu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwsub-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwsub-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwsub.w-rv32.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwsub.w-rv64.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwsubu-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwsubu-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vwsubu.w-rv32.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vwsubu.w-rv64.ll [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv. 2021-06-01 18:59:00 -07:00
vxor-rv32.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00
vxor-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vxor-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vxor-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vxor-vp.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vzext-rv32.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
vzext-rv64.ll [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
wrong-stack-slot-rv32.mir [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
wrong-stack-slot-rv64.mir [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
zvlsseg-copy.mir [RISCV][NFC] Add '+mattr=+experimental-v' to RVV test 2021-06-02 13:09:13 +01:00
zvlsseg-spill.mir [RISCV] Use X0 as destination of inserted vsetvli when possible. 2021-05-26 13:08:51 -07:00
zvlsseg-zero-vl.ll [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. 2021-05-27 10:11:38 -07:00