forked from OSchip/llvm-project
ce3d1c6d61
Summary: Add unwinding support for 64-bit RISC-V. This is from the FreeBSD implementation with the following minor changes: - Renamed and renumbered DWARF registers to match the RISC-V ABI [1] - Use the ABI mneumonics in getRegisterName() instead of the exact register names - Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit ABI in the future. [1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md Patch by Mitchell Horne (mhorne) Reviewers: lenary, luismarques, compnerd, phosek Reviewed By: lenary, luismarques Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D68362 |
||
|---|---|---|
| .. | ||
| cmake | ||
| docs | ||
| include | ||
| src | ||
| test | ||
| .arcconfig | ||
| .clang-format | ||
| CMakeLists.txt | ||
| LICENSE.TXT | ||