llvm-project/llvm/test/CodeGen
Peter Collingbourne 78f1ecc59c ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.
This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

llvm-svn: 235637
2015-04-23 20:31:26 +00:00
..
AArch64 [AArch64] Add nvcast patterns for v4f16 and v8f16 2015-04-23 17:32:25 +00:00
ARM ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. 2015-04-23 20:31:26 +00:00
BPF [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
CPP [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Generic Re-commit r235560: Switch lowering: extract jump tables and bit tests before building binary tree (PR22262) 2015-04-23 16:45:24 +00:00
Hexagon [Hexagon] Shrink-wrap stack frame (Hexagon-specific) 2015-04-23 16:05:39 +00:00
Inputs DebugInfo: Fix bad debug info for compile units and types 2015-03-27 20:46:33 +00:00
MSP430 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
Mips Fix correctness check for test_vec_fpextend_double 2015-04-22 18:04:12 +00:00
NVPTX [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
PowerPC [PowerPC] Enable printing instructions using aliases 2015-04-23 18:30:38 +00:00
R600 R600: Fix always inline pass breaking noinline functions 2015-04-22 17:10:44 +00:00
SPARC [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
SystemZ Allow memory intrinsics to be tail calls 2015-04-13 17:16:45 +00:00
Thumb [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Thumb2 ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. 2015-04-23 20:31:26 +00:00
WinEH Revert "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works" 2015-04-23 18:34:01 +00:00
X86 Revert "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare works" 2015-04-23 18:34:01 +00:00
XCore [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00