llvm-project/llvm/test/CodeGen
Chandler Carruth 2ce191e220 [x86] Fix a really subtle miscompile due to a somewhat glaring bug in
EFLAGS copy lowering.

If you have a branch of LLVM, you may want to cherrypick this. It is
extremely unlikely to hit this case empirically, but it will likely
manifest as an "impossible" branch being taken somewhere, and will be
... very hard to debug.

Hitting this requires complex conditions living across complex control
flow combined with some interesting memory (non-stack) initialized with
the results of a comparison. Also, because you have to arrange for an
EFLAGS copy to be in *just* the right place, almost anything you do to
the code will hide the bug. I was unable to reduce anything remotely
resembling a "good" test case from the place where I hit it, and so
instead I have constructed synthetic MIR testing that directly exercises
the bug in question (as well as the good behavior for completeness).

The issue is that we would mistakenly assume any SETcc with a valid
condition and an initial operand that was a register and a virtual
register at that to be a register *defining* SETcc...

It isn't though....

This would in turn cause us to test some other bizarre register,
typically the base pointer of some memory. Now, testing this register
and using that to branch on doesn't make any sense. It even fails the
machine verifier (if you are running it) due to the wrong register
class. But it will make it through LLVM, assemble, and it *looks*
fine... But wow do you get a very unsual and surprising branch taken in
your actual code.

The fix is to actually check what kind of SETcc instruction we're
dealing with. Because there are a bunch of them, I just test the
may-store bit in the instruction. I've also added an assert for sanity
that ensure we are, in fact, *defining* the register operand. =D

llvm-svn: 338481
2018-08-01 03:01:58 +00:00
..
AArch64 [GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate. 2018-08-01 02:17:42 +00:00
AMDGPU AMDGPU: Add clamp bit to dot intrinsics 2018-08-01 01:31:30 +00:00
ARC
ARM Revert r338354 "[ARM] Revert r337821" 2018-07-31 23:09:42 +00:00
AVR [AVR] Set trackLivenessAfterRegAlloc 2018-06-11 14:46:48 +00:00
BPF bpf: add missing RegState to notify MachineInstr verifier necessary register usage 2018-07-27 16:58:52 +00:00
Generic Implement strip.invariant.group 2018-07-02 04:49:30 +00:00
Hexagon [Hexagon] Simplify A4_rcmp[n]eqi R, 0 2018-07-30 14:28:02 +00:00
Inputs
Lanai
MIR [DebugInfo][X86] Add start-after flags to MIR tests 2018-07-12 14:36:48 +00:00
MSP430
Mips [DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B) 2018-07-28 00:27:25 +00:00
NVPTX finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests 2018-07-11 20:31:51 +00:00
Nios2
PowerPC [DAGCombiner] transform sub-of-shifted-signbit to add 2018-07-30 22:21:37 +00:00
RISCV [RISCV] Fixed test case failure due to r338047 2018-07-31 00:36:28 +00:00
SPARC Regenerate remainder test. 2018-07-20 13:14:29 +00:00
SystemZ [SystemZ] Improve decoding in case of instructions with four register operands. 2018-07-31 13:00:42 +00:00
Thumb [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1. 2018-07-25 18:22:22 +00:00
Thumb2 [ARM] Treat cmn immediates as legal in isLegalICmpImmediate. 2018-07-10 23:44:37 +00:00
WebAssembly Revert "[WebAssembly] Added default stack-only instruction mode for MC." 2018-07-27 23:19:51 +00:00
WinCFGuard
WinEH
X86 [x86] Fix a really subtle miscompile due to a somewhat glaring bug in 2018-08-01 03:01:58 +00:00
XCore [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) 2018-07-15 16:27:07 +00:00