forked from OSchip/llvm-project
89 lines
3.8 KiB
LLVM
89 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx2 | FileCheck %s
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; Test that we correctly fold a shuffle that performs a swizzle of another
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; shuffle node according to the rule
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; shuffle (shuffle (x, undef, M0), undef, M1) -> shuffle(x, undef, M2)
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;
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; We only do this if the resulting mask is legal to avoid introducing an
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; illegal shuffle that is expanded into a sub-optimal sequence of instructions
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; during lowering stage.
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; Check that we produce a single vector permute / shuffle in all cases.
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define <8 x i32> @swizzle_1(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_1:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [1,3,2,0,4,5,6,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 3, i32 1, i32 2, i32 0, i32 7, i32 5, i32 6, i32 4>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 7, i32 5, i32 6, i32 4>
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ret <8 x i32> %2
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}
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define <8 x i32> @swizzle_2(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
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ret <8 x i32> %2
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}
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define <8 x i32> @swizzle_3(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_3:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
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ret <8 x i32> %2
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}
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define <8 x i32> @swizzle_4(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_4:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [3,1,2,0,6,5,4,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 4, i32 7, i32 5, i32 6, i32 3, i32 2, i32 0, i32 1>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 4, i32 7, i32 5, i32 6, i32 3, i32 2, i32 0, i32 1>
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ret <8 x i32> %2
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}
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define <8 x i32> @swizzle_5(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_5:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [3,0,1,2,7,6,4,5]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 7, i32 4, i32 6, i32 5, i32 0, i32 2, i32 1, i32 3>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 7, i32 4, i32 6, i32 5, i32 0, i32 2, i32 1, i32 3>
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ret <8 x i32> %2
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}
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define <8 x i32> @swizzle_6(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_6:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [3,1,0,2,4,5,6,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 2, i32 1, i32 3, i32 0, i32 4, i32 7, i32 6, i32 5>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 2, i32 1, i32 3, i32 0, i32 4, i32 7, i32 6, i32 5>
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ret <8 x i32> %2
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}
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define <8 x i32> @swizzle_7(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_7:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [0,2,3,1,4,5,6,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 0, i32 3, i32 1, i32 2, i32 5, i32 4, i32 6, i32 7>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 0, i32 3, i32 1, i32 2, i32 5, i32 4, i32 6, i32 7>
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ret <8 x i32> %2
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}
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