forked from OSchip/llvm-project
81 lines
1.6 KiB
LLVM
81 lines
1.6 KiB
LLVM
; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
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; CHECK-LABEL: fn1
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define signext i32 @fn1(i32 %baz) {
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%1 = mul nsw i32 %baz, 208
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%2 = zext i32 %1 to i64
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%3 = shl i64 %2, 48
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%4 = ashr exact i64 %3, 48
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; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
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; CHECK: CMPLDI
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; CHECK: BCC
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; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
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; CHECK: COPY %CR0
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; CHECK: BCC
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%5 = icmp eq i64 %4, 0
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br i1 %5, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; CHECK-LABEL: fn2
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define signext i32 @fn2(i64 %a, i64 %b) {
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; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>;
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; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
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; CHECK: BCC 12, [[CREG]]<kill>
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%1 = or i64 %b, %a
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%2 = icmp sgt i64 %1, -1
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br i1 %2, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; CHECK-LABEL: fn3
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define signext i32 @fn3(i32 %a) {
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; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>;
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; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
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; CHECK: BCC 76, [[CREG]]<kill>
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%1 = and i32 %a, 10
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; This test case confirms that a record-form instruction is
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; generated even if the branch has a static branch hint.
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; CHECK-LABEL: fn4
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define i64 @fn4(i64 %a, i64 %b) {
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; CHECK: ADD8o
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; CHECK-NOT: CMP
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; CHECK: BCC 71
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entry:
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%add = add nsw i64 %b, %a
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%cmp = icmp eq i64 %add, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @exit(i32 signext 0) #3
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unreachable
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if.end:
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ret i64 %add
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}
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declare void @exit(i32 signext)
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