forked from OSchip/llvm-project
110 lines
4.2 KiB
C++
110 lines
4.2 KiB
C++
//===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that VE uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H
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#define LLVM_LIB_TARGET_VE_VEISELLOWERING_H
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#include "VE.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class VESubtarget;
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namespace VEISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Hi,
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Lo, // Hi/Lo operations, typically on a global address.
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GETFUNPLT, // load function address through %plt insturction
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GETTLSADDR, // load address for TLS access
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GETSTACKTOP, // retrieve address of stack top (first address of
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// locals and temporaries)
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CALL, // A call instruction.
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RET_FLAG, // Return with a flag operand.
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GLOBAL_BASE_REG, // Global base reg for PIC.
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};
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}
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class VETargetLowering : public TargetLowering {
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const VESubtarget *Subtarget;
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public:
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VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
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const char *getTargetNodeName(unsigned Opcode) const override;
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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return MVT::i32;
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}
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
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SelectionDAG &DAG) const override;
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/// Custom Lower {
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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/// } Custom Lower
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SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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SelectionDAG &DAG) const;
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SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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/// Returns true if the target allows unaligned memory accesses of the
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/// specified type.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
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MachineMemOperand::Flags Flags,
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bool *Fast) const override;
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// Block s/udiv lowering for now
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bool isIntDivCheap(EVT VT, AttributeList Attr) const override { return true; }
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bool hasAndNot(SDValue Y) const override;
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};
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} // namespace llvm
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#endif // VE_ISELLOWERING_H
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