forked from OSchip/llvm-project
62 lines
2.5 KiB
TableGen
62 lines
2.5 KiB
TableGen
//=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class HexagonV67TPseudoItin {
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list<InstrItinData> V67TPseudoItin_list = [
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InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
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[2, 1, 1]>,
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InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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];
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}
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// V67TItin_list and HVXItin contain some old itineraries
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// still used by a handful of instructions. Hopefully, we will be able to
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// get rid of them soon.
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def HexagonV67TItinList : DepScalarItinV67T,
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DepHVXItinV67, HVXItin, HexagonV67TPseudoItin {
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list<InstrItinData> V67TItin_list = [
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InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
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[3, 1, 1],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
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[1, 1, 3, 3],
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[Hex_FWD, Hex_FWD]>
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];
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list<InstrItinData> ItinList =
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!listconcat(DepScalarItinV67T_list,
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DepHVXItinV67_list, V67TItin_list,
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HVXItin_list, V67TPseudoItin_list);
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}
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def HexagonItinerariesV67T :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
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CVI_ALL_NOMEM, CVI_ZW],
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[Hex_FWD, HVX_FWD],
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HexagonV67TItinList.ItinList>;
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def HexagonModelV67T : SchedMachineModel {
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let IssueWidth = 3;
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let Itineraries = HexagonItinerariesV67T;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V67 Tiny Core Resource Definitions -
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//===----------------------------------------------------------------------===//
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