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llvm-project/llvm/lib/Target/AArch64
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Francis Visoiu Mistrih c855e92ca9 [AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true 
Put the first ldp at the end, so that the load-store optimizer can run
and merge the ldp and the add into a post-index ldp.

This didn't work in case no frame was needed and resulted in code size
regressions.

llvm-svn: 331044
 		2018-04-27 15:30:54 +00:00
..
AsmParser [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions. 2018-04-26 12:54:42 +00:00
Disassembler [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions. 2018-04-20 12:52:01 +00:00
InstPrinter [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes. 2018-04-25 09:26:47 +00:00
MCTargetDesc Recommit r329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation" 2018-04-10 19:46:43 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
Utils [AArch64][SVE] Asm: Predicate patterns 2018-01-22 10:46:00 +00:00
AArch64.h [AArch64] Avoid SIMD interleaved store instruction for Exynos. 2017-12-08 00:58:49 +00:00
AArch64.td [PATCH] [AArch64] Add new target feature to fuse conditional select 2018-02-23 19:27:43 +00:00
AArch64A53Fix835769.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64A57FPLoadBalancing.cpp [AArch64] Change std::sort to llvm::sort in response to r327219 2018-04-04 18:20:28 +00:00
AArch64AdvSIMDScalarPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64AsmPrinter.cpp [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64 2018-01-17 23:55:23 +00:00
AArch64CallLowering.cpp [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer. 2018-03-29 17:21:10 +00:00
AArch64CallLowering.h GlobalISel (AArch64): fix ABI at border between GPRs and SP. 2017-08-21 21:56:11 +00:00
AArch64CallingConvention.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td AArch64: Implement support for the shadowcallstack attribute. 2018-04-04 21:55:44 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print" 2018-02-19 15:08:49 +00:00
AArch64CondBrTuning.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ConditionOptimizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ConditionalCompares.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64DeadRegisterDefinitionsPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str 2018-03-12 18:47:43 +00:00
AArch64FalkorHWPFFix.cpp [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass. 2018-04-10 21:43:03 +00:00
AArch64FastISel.cpp [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer. 2018-03-29 17:21:10 +00:00
AArch64FrameLowering.cpp [AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true 2018-04-27 15:30:54 +00:00
AArch64FrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
AArch64GenRegisterBankInfo.def [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies 2017-11-18 04:28:56 +00:00
AArch64ISelDAGToDAG.cpp Reland r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses.", with a fix for the bot failure. 2018-04-23 19:09:34 +00:00
AArch64ISelLowering.cpp Reland r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses.", with a fix for the bot failure. 2018-04-23 19:09:34 +00:00
AArch64ISelLowering.h [AArch64] Don't reduce the width of loads if it prevents combining a shift 2018-03-23 14:47:07 +00:00
AArch64InstrAtomics.td [AArch64] Improve v8.1-A code-gen for atomic load-and 2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td [AArch64] Codegen for v8.2A dot product intrinsics 2018-04-27 13:45:32 +00:00
AArch64InstrInfo.cpp [MachineOutliner] Don't outline from functions with a section marking. 2018-04-27 00:21:34 +00:00
AArch64InstrInfo.h [MachineOutliner] Add `useMachineOutliner` target hook 2018-04-04 19:13:31 +00:00
AArch64InstrInfo.td [AArch64] Codegen for v8.2A dot product intrinsics 2018-04-27 13:45:32 +00:00
AArch64InstructionSelector.cpp [AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic. 2018-04-25 14:43:59 +00:00
AArch64LegalizerInfo.cpp [globalisel][legalizerinfo] Add support for the Lower action in getActionDefinitionsBuilder() and use it in AArch64. 2018-04-09 21:10:09 +00:00
AArch64LegalizerInfo.h [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal 2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp [CodeGen] Add a new pass for PostRA sink 2018-03-22 20:06:47 +00:00
AArch64MCInstLower.cpp Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64MCInstLower.h [COFF, ARM64] Add support for Windows ARM64 COFF format 2017-06-27 23:58:19 +00:00
AArch64MachineFunctionInfo.h [MachineOutliner] Keep track of fns that use a redzone in AArch64FunctionInfo 2018-04-03 21:56:10 +00:00
AArch64MacroFusion.cpp [PATCH] [AArch64] Add new target feature to fuse conditional select 2018-02-23 19:27:43 +00:00
AArch64MacroFusion.h Recommit rL305677: [CodeGen] Add generic MacroFusion pass 2017-06-19 12:53:31 +00:00
AArch64PBQPRegAlloc.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PromoteConstant.cpp [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64RedundantCopyElimination.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64RegisterBankInfo.cpp [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h [AArch64][RegisterBankInfo] Add mapping for G_FPEXT. 2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td [aarch64][globalisel] Register banks and classes should have distinct names. 2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp AArch64: Implement support for the shadowcallstack attribute. 2018-04-04 21:55:44 +00:00
AArch64RegisterInfo.h [AArch64] Implement dynamic stack probing for windows 2018-02-17 14:26:32 +00:00
AArch64RegisterInfo.td [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes. 2018-04-25 09:26:47 +00:00
AArch64SIMDInstrOpt.cpp [TargetSchedule] shrink interface for init(); NFCI 2018-04-08 19:56:04 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions. 2018-04-26 08:19:53 +00:00
AArch64SchedA53.td [AArch64] Clean-up a few over-eager regexps in models. 2018-03-23 11:00:42 +00:00
AArch64SchedA57.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedExynosM1.td [AArch64][NFC] Make all ProcResource definitions include their SchedModel. 2018-02-01 12:12:01 +00:00
AArch64SchedExynosM3.td [AArch64] Adjust the cost model for Exynos M3 2018-04-03 22:57:17 +00:00
AArch64SchedFalkor.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Correct load/store increment scheduling details 2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination. 2017-06-19 21:57:42 +00:00
AArch64SchedThunderX.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedThunderX2T99.td [AArch64] Clean-up a few over-eager regexps in models. 2018-03-23 11:00:42 +00:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp AArch64/X86: Factor out common bzero logic; NFC 2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
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AArch64StorePairSuppress.cpp [TargetSchedule] shrink interface for init(); NFCI 2018-04-08 19:56:04 +00:00
AArch64Subtarget.cpp AArch64: Implement support for the shadowcallstack attribute. 2018-04-04 21:55:44 +00:00
AArch64Subtarget.h [PATCH] [AArch64] Add new target feature to fuse conditional select 2018-02-23 19:27:43 +00:00
AArch64SystemOperands.td [AArch64] Fix spelling of ICH_ELRSR_EL2 system register 2018-02-06 09:39:04 +00:00
AArch64TargetMachine.cpp MachO: trap unreachable instructions 2018-04-13 22:25:20 +00:00
AArch64TargetMachine.h (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp Move Object format code to lib/BinaryFormat. 2017-06-07 03:48:56 +00:00
AArch64TargetObjectFile.h Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp [TTI, AArch64] Add transpose shuffle kind 2018-04-26 13:48:33 +00:00
AArch64TargetTransformInfo.h [TTI, AArch64] Add transpose shuffle kind 2018-04-26 13:48:33 +00:00
CMakeLists.txt Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt 2018-04-23 12:49:34 +00:00
LLVMBuild.txt
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SVEInstrFormats.td [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions. 2018-04-26 08:19:53 +00:00